STA529
Registers
S2PCFG0
Serial-to-parallel audio interface configuration
register 0
Bit 7
BICLK_STRB
Bit 6
LRCLK_LEFT
Bit 5
SHARE_BILR
Bit 4
MSB_FIRST
Bit 3
Bit 2
DATA_FORMAT[2:0]
Bit 1
Bit 0
MASTER_
MODE
Address:
0x0A
Type:
R/W
Buffer:
No
Reset:
0xD2
Description:
7 BICLK_STRB:
0: bit clock strobe edge is falling edge, bit clock active edge is rising edge
1: bit clock strobe edge is rising edge, bit clock active edge is falling edge (default)
6 LRCLK_LEFT:
0: left/right clock is low for left channel, high for right channel
1: left/right clock is high for left channel, low for right channel (default)
5 SHARE_BILR:
0: default
1: left/right clock and bit clock are shared between serial-parallel interface and parallel-to-
serial interface, BICLKI and LRCLKI are used
4 MSB_FIRST:
0: LSB first
1: MSB first (default)
3:1 DATA_FORMAT[2:0]: serial interface protocol format:
000: left Justified
001: I2S (default)
010: right justified
100: PCM no delay
101: PCM delay
111: DSP
001: default
0 MASTER_MODE:
0: default
1: serial interface is in master mode
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