STK16C88-3 查看數據表（PDF） - Unspecified
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STK16C88-3 Datasheet PDF : 11 Pages
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STK16C88-3
SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
#1
#2
Alt.
PARAMETER
12
tAVAV
tAVAV
tWC Write Cycle Time
13
tWLWH
tWLEH
tWP Write Pulse Width
14
tELWH
tELEH
tCW Chip Enable to End of Write
15
tDVWH
tDVEH
tDW Data Set-up to End of Write
16
tWHDX
tEHDX
tDH Data Hold after End of Write
17
tAVWH
tAVEH
tAW Address Set-up to End of Write
18
tAVWL
tAVEL
tAS Address Set-up to Start of Write
19
tWHAX
tEHAX
20
tWLQZ h, i
tWR Address Hold after End of Write
tWZ Write Enable to Output Disable
21
tWHQX
tOW Output Active after End of Write
Note i: If W is low when E goes low, the outputs remain in the high-impedance state.
Note j: E or W must be ≥ VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledj
ADDRESS
12
tAVAV
14
tELWH
E
W
DATA IN
DATA OUT
18
tAVWL
17
tAVWH
13
tWLWH
20
tWLQZ
PREVIOUS DATA
15
tDVWH
DATA VALID
HIGH IMPEDANCE
SRAM WRITE CYCLE #2: E Controlledj
ADDRESS
E
18
tAVEL
12
tAVAV
14
tELEH
(VCC = 3.0V-3.6V)
STK16C88-3-35
MIN
MAX
35
UNITS
ns
25
ns
25
ns
12
ns
0
ns
25
ns
0
ns
0
ns
13
ns
5
ns
19
tWHAX
16
tWHDX
21
tWHQX
19
tEHAX
W
DATA IN
DATA OUT
17
tAVEH
13
tWLEH
15
tDVEH
DATA VALID
HIGH IMPEDANCE
16
tEHDX
March 2006
4 Document Control # ML0019 rev 0.2
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