STW5094AD 查看數據表（PDF） - STMicroelectronics

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STW5094AD

18-bit Low Power Asynchronous Stereo Audio DAC with Integrated Power Amplifiers and Voice Codec

STMicroelectronics 

STw5094A

2.11 Buzzer Output

The output BZ is intended to drive a Buzzer, via an external BJT, with a squarewave pulse width modu-

lated (PWM) signal. The frequency of the signal is stored in CR13 (see Tone Generator section and

Table 1 for frequency values). For some applications it is also possible to multiply this PWM signal with a

squarewave signal having a frequency stored in CR14. The duty cycle of the buzzer output can be varied

in CR15 in order to change the buzzer volume. Maximum load for BZ is 5kΩ and 50pF

2.12 Voice Data Interface (PCM I⁄ F)

The PCM I⁄ F is used to exchange the Voice data in both TX and RX direction, it can be programmed for

linear format data or companded A-law or µ-law format (see Fig.1, 2 and 3).

Frame Sync input FS determines the beginning of frame. It may have any duration from a single cycle of

MCLK to a squarewave. Three different relationships may be established between the Frame Sync input

and the first time slot of the frame by setting bits DM in CR1. In non delayed normal and reverse data mode

(long frame timing) the first time slot starts at the rising edge of FS. In delayed data mode (short frame

sync timing) FS input must be high for at least a half cycle of MCLK before the frame start.

When linear code is selected (bit CM = 0 in CR0) the MSB is transmitted and received first, the word length

is 16 bit. When companded code is selected (bit CM = 1 in CR0) a time slot assignment may be used in

all timing modes (bit TS in CR1), that allows connection to one of the two B1 and B2 voice data channels.

Two data formats are available: in Format 1, time slot B1 corresponds to the 8 MCLK cycles that immedi-

ately follow the rising edge of FS, while time slot B2 corresponds to the 8 MCLK cycles that immediately

follow time slot B1. In Format 2, time slot B1 is identical to Format 1 while time slot B2 appears two bit

slots after time slot B1. This two bits space is left available for insertion of the D channel data. Data format

is selected by bit FF in CR0.

Bit EN in CR1 enables or disables data transfer on DX and DR.

Outside the selected time slot DX is in the high impedance condition. During the selected time slot the DX

output and the DR input are synchronized as follow:

-If delayed or non-delayed modes are selected the transmit voice data is sent to DX output on the

rising edges of MCLK and receive voice data is read at DR input on the falling edges of MCLK.

-If non-delayed reverse mode is selected the transmit voice data register is sent to DX output on the

falling edges of MCLK and receive voice data is read at DR input on the rising edges of MCLK.

When 16kHz Frame Sync frequency is selected (bit VFS in CR0) the RX and TX filters are both low-pass

and their cutoff frequencies are doubled.

It is possible to access the B channel data when companded A-law or µ-law formats are used (bits MX and

MR in CR1). A byte written into CR3A will be sent to DX output in place of the transmit channel PCM data.

A byte written in CR2A will be sent to the receive path. The current byte received on DR input can be read

in CR2A.

2.13 Audio Data Interface (Au I⁄ F)

The Au I⁄ F is used to receive the Stereo Audio data. The pins related to the Au I⁄ F are: the frame syn-

chronism or Left/Right indicator LRCK, the serial bit clock SCK, and the serial data input SDI. LRCK and

SCK can be input or output depending if the Au I⁄ F is configured in Slave or Master mode.

The interface can be configured in 5 different modes programming bits SPIM, MSM and DSPM in CR17.

In each mode different parameters (word length, signal polarity etc.) can be set writing CR16.

The MSM bit selects if Au I ⁄ F is Master or Slave. When MSM=0 the Au I ⁄ F is Slave: the serial bit clock

SCK and the frame sync LRCK are input to the device. When MSM=1 the Au I ⁄ F is Master: SCK and

LRCK are generated inside the device. The frequency of LRCK is programmed in CR2B and CR3B while

its shape and the frequency of SCK change automatically with the selected mode (see paragraph below).

Master mode is not available when the Au I ⁄ F is configured in SPI-mode (SPIM=1) regardless of the

value of MSM.

The 5 possible mode modes are:

I2S-Mode Slave (SPIM=0, MSM=0 and DSPM=0) in this mode the Au I ⁄ F is I2S compatible (see Fig. 5

and 10) and the bit clock SCK and the left/right indicator LRCK signals are input to the device. SCK must

have 16 periods per channel in case of 16bit data word and 32 periods per channel in case of 18bit to 24bit

data word. SCK can be either a continuous clock or a sequence of bursts.

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