STW5094AD 查看數據表（PDF） - STMicroelectronics

零件编号

产品描述 (功能)

生产厂家

STW5094AD

18-bit Low Power Asynchronous Stereo Audio DAC with Integrated Power Amplifiers and Voice Codec

STMicroelectronics 

STw5094A

I2S-Mode Master (SPIM=0, MSM=1 and DSPM=0) this mode is functionally equivalent to I2S-mode Slave

(see Fig. 7 and 10) but the bit clock SCK and the left/right indicator LRCK signals are generated by the

device. SCK is generated with 16 periods per channel in case of 16bit data word and 32 periods per chan-

nel in case of 18bit to 24bit data word

DSP-Mode Slave (SPIM=0, MSM=0 and DSPM=1) in this mode the Au I ⁄ F starting from a frame sync

pulse on LRCK receives the Left and Right data one after the other (see Fig. 6 and 11). SCK is a free

running bit clock: between 2 successive frame sync pulse there can be any number of SCK periods from

the minimum necessary to transfer all the data bits up to the max. frequency limit specified for SCK. DSP-

mode is suited to interface with a Master Multi-Byte Serial Interface.

DSP-Mode Master (SPIM=0, MSM=1 and DSPM=1) this mode is functionally equivalent to DSP-mode

Slave but LRCK and SCK signals are generated by the device (see Fig. 8 and 12). SCK is generated with

32 periods per frame sync. in case of 16bit data word and 64 periods per frame sync. in case of 18bit to

24bit data word. DSP-mode Master is suited to interface with a Slave Multi-Byte Serial Interface.

SPI-Mode (SPIM=1 and DSPM=0) in this mode Left and Right data are received with separate data burst.

Every burst is identified with a low level on LRCK signal (see Fig. 9 and 13). There is no timing difference

between the Left and Right data burst: the two channels are identified by the fact that the first burst after

Audio mode power-up identifies the Left channel data and the second one is the Right channel data and

then Left and Right data repeat one after the other. SCK must have 16 periods per channel in case of 16bit

data word and 32 periods per channel in case of 18bit to 24bit data word. SPI-mode can only be Slave:

when SPIM=1 the values written on MSM is disregarded while DSPM must be set to 0.

In some of the above listed modes not all the combinations of the bits in CR16 are available or meaningful:

- In DSP-Mode MSB is always received first (bit ORD=0), data word justification and LRCK polarity

have no meaning.

- In SPI-mode the data word must be always left-justified (bit DIF=0) and non-delayed (bit FOR=1) and

LRCK polarity must be always set for Left=0 (INV=0).

The audio data sample rate (LRCK frequency) can be any value in the range 8kHz to 48kHz.

Left channel data are always received first.

The first 35 Data frames after power up are discarded while the interpolation filters data memory is

cleared.

2.14 LRCK & SCK generation in Master Mode

Setting MSM=1 and SPIM=0 in CR17 enables the internal generation of the frame synchronism clock

LRCK and of the serial bit clock SCK.

These clocks are obtained by variable division from the AMCK system clock. Given the AMCK frequency

(fAMCK), the desired sample rate frequency (fLRCK) is obtained by writing in CR2B the least significant byte

and in CR3B the most significant byte of the16bit integer result calculated with the following formula:

N = round(223·(fLRCK ⁄ fAMCK))

The precision of the obtained fLRCK is always better than ±1.7Hz.

The shape of LRCK waveform and the number of SCK periods for each LRCK period is set automatically

depending on the values of bit DSPM in CR17 and of CR16 content (see Fig. 7,8,10 and 12).

Since CR2B and CR3B are overlaid registers, In order to write the division factor N in CR2B and CR3B

the master mode must be selected in advance by setting MSM=1.

NOTE: LRCK and SCK are part of the Au I ⁄ F, but Master mode generation can also be used as Frame

Sync and Master clock in Voice Mode by connecting them to FS and MCLK (in this case a fixed clock on

AMCK is needed).

12/51

Share Link: