TDA9203 查看數據表（PDF） - STMicroelectronics

零件编号

产品描述 (功能)

生产厂家

TDA9203

I²C BUS CONTROLLED 70MHz RGB PREAMPLIFIER

STMicroelectronics 

TDA9203A

FUNCTIONAL DESCRIPTION

Input Stage

The R, G and B signals must be fed to the three

inputs through coupling capacitors (100nF).

The maximum input peak-to-peak video amplitude

is 1V.

The input stage includes a clamping function. This

clamp is using the input serial capacitor as ”mem-

ory capacitor” and is gated by an internally gener-

ated ”Back-Porch-Clamping-Pulse (BPCP)”.

The synchronization edge of the BPCP is selected

according bit 0 of register R8.

When B0R8 is set to 1, the BPCP is synchronized

on the leadingedgeof the blankingpulse BLKinputs

on Pin14 (seeFigure1). B7R8 allowsto usepositive

or negative blanking signal on Pin 14. At power on

reset TDA9203Ause only positive blanking.

Figure 1

BLK

HSYNC

BPCP

Internal pulse width is controlled by I2C

When B0R8 is clear to 0, the BPCP is synchronized

on the second edge of the horizontal pulse HSYNC

inputs on Pin 24. An automatic function allows to

use positive or negative horizontal pulse on Pin 24

(see Figure 2).

Figure 2

HSYNC

BPCP

Internal pulse width is controlled by I2C

In both case BPCP width is adjustable by I2C, B1

and B2 of register R8 (see R8 Table P8).

Contrast Adjustment (8 bits)

The contrast adjustment is made by controlling

simultaneously the gain of three internal variable

gain amplifiers through the I2C bus interface.

The contrast adjustment allows to cover a typical

range of 48dB.

ABL Control

The TDA9203A I2C preamplifier provides an ABL

input (automatic beam limitation) to attenuate

R,G,B video signals according to beam intensity.

The operating range is 2.5V typicaly, from 5.3V to

2.8V. A typical 12dB Max. attenuationis applied to

the signal whatever the current gain is. Refer to

Figure 3 for ABL input attenuation range.

In case of software control, the ABL input must be

pulled to AVDD through a resistor to limit power

consumption (see Figure 11).

ABL input voltage must not exceeed AVDD. Input

resistor is 10kΩ and equivalent schematic given in

Figure 11.

Figure 3

Attenuation (dB)

2

0

-2

-4

-6

-8

-10

-12

VIN (V)

-14

123456789

Brightness Adjustment (8 bits)

As for the contrast adjustment, the brightness is

controlled by I2C.

The brightness function consists to add the same

DC offset to the three R, G, B signals after contrast

amplification. This DC-Offset is present only out-

side the blanking pulse (see Figure 4).

The DC output level during the blanking pulse, is

forced to ”INFRA-BLACK” level (VDC).

Drive Adjustment (3 x 8 bits)

In order to adjust the white balance, the TDA9203A

offers the possibility to adjust separatelythe overall

gain of each complete video channel. The gain of

each channel is controlled by I2C (8bits each).

The very large drive adjustment range(48dB) allows

different standard or custom color temperature.

It can also be used to adjust the output voltages at

the optimum amplitude to drive the C.R.T drivers,

keepingthe whole contrast control for end-useronly.

The drive adjustment is located after the CON-

TRAST, BRIGHTNESS and OSD switch blocks, so

that the white balance will remains correct when

BRT is adjusted, and will also be correct on OSD

portion of the signal.

3/13

Share Link: