N80C51GB 查看數據表（PDF） - Intel

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N80C51GB

CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

Intel 

8XC51GB

Sample Window Begins when the sample capaci-

tor is attached to a selected channel and ends when

the sample capacitor is disconnected from the se-

lected channel

Successive Approximation An A D conversion

method which uses a binary search to arrive at the

best digital representation of an analog input

Temperature Coefficients Change in the stated

variable per degree centrigrade temperature

change Temperature coefficients are added to the

typical values of a specification to see the effect of

temperature drift

Terminal Based Characteristic An actual charac-

teristic which has been rotated and translated to re-

move zero offset and full scale error

VCC Rejection Attenuation of noise on the VCC

line to the A D converter

Zero Offset The difference between the expected

and actual input voltage corresponding to the first

code transition

DATA SHEET REVISION SUMMARY

The following differences exist between this data-

sheet and the previous version (270869-003)

1 Merged 87C51GB Express (270889-001)

2 New order number 272337-001

The following differences exist between the 270869-

003 data sheet and the previous version (270869-

002)

1 Changed data sheet status from ‘‘Advance Infor-

mation’’ to ‘‘Preliminary’’ and updated associated

notices

2 Added 83C51GB throughout

3 Added Package and Process Information

4 Clarified g2 LSB accuracy for channels 0 and 1

in A D Converter Section

5 Added ‘‘ROM and EPROM Lock System’’ section

and added 83C51GB to ‘‘Program Lock Bits’’

section

6 Modified Signature Bytes Table

The following differences exist between the

270869-002 data sheet and the previous version

(270869-001)

1 Changed data sheet status from ‘‘Product Pre-

view’’ to ‘‘Advance Information’’ and updated as-

sociated notices

2 Asynchronous port reset was added to RESET

pin description

3 ALE disable paragraph was added to ALE pin de-

scription

4 C1 C2 guidelines clarified in Figure 4

5 Operating Conditions heading was added

6 Maximum IOL per I O pin was added to Absolute

Maximum Ratings

7 VTa VTb VHYS VOL2 and VTL removed

8 VOL value for ALE included with VOL1

9 VIL1 and VIL2 added

10 RRST minimum changed from 40K to 50K

RRST maximum changed from 225K to 300K

11 IPD maximum changed from 200 mA to 50 mA

12 IDL maximum changed from 15 mA to 18 mA

13 Typical values for IPD IDL ICC and IREF re-

moved

14 Note 3 (page 9) was reworded

15 SEP AC Timings added

16 A D Absolute Error for Channels 0 and 1

changed to g2 LSB

17 TCY clarified

18 Encryption array paragraph was added

19 Corrected pin numbers on Figure 11 to reflect

PLCC package

22

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