84068012A(1997) 查看數據表（PDF） - Intersil

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84068012A
(Rev.:1997)

CMOS Clock Generator Driver

Intersil 

Timing Waveforms

82C84A

NAME I/O

EFI I

OSC O

CLK O

PCLK O

CSYNC I

RES I

RESET O

(3)

tELEL

(13)

tEHYL

(14)

tYHYL

tOLCH

(29)

tCH1CH2

(20)

tYHEH

(12)

tCL2CL1

(21)

(30)

tOLCL

tELEH

(2)

(1) tEHEL

tCLPH

(27)

tPLPH

(23)

(19)

tCLCH

(17) tCLCL

(22)

tPHPL

(16)

(15)

tCLI1H tI1HCL

tCHCL

(18)

tCLPL

(28)

(26)

tCLIL

NOTE: All timing measurements are made at 1.5V, unless otherwise noted.

FIGURE 2. WAVEFORMS FOR CLOCKS AND RESETS SIGNALS

CLK

tCLR1X

(7)

tR1VCH

RDY1, 2

(5)

(10)

tA1VR1V

AEN1, 2

ASYNC

tAYVCL

(8)

tCLAYX

(9)

READY

(25)

tRYHCH

tCLR1X

tR1VCL

(6)

(7)

tCLA1X

(11)

(24) tRYLCL

FIGURE 3. WAVEFORMS FOR READY SIGNALS (FOR ASYNCHRONOUS DEVICES)

CLK

RDY 1, 2

AEN1, 2

ASYNC

tCLR1X

(7)

(4) tR1VCL

tA1VRIV (10)

(8) tAYVCL

tCLAYX

(9)

READY

(25)

tRYHCH

tCLR1X

(7)

tCLA1X

(11)

tR1VCL

(6)

(24)

tRYLCL

FIGURE 4. WAVEFORMS FOR READY SIGNALS (FOR SYNCHRONOUS DEVICES)

4-293

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