UC1608XFAC 查看數據表（PDF） - Unspecified

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UC1608XFAC

128x240 Matrix LCD Controller-Drivers

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UC1608

128x240 Matrix LCD Controller-Drivers

HOST INTERFACE

As summarized in the table below, UC1608

supports two parallel bus protocols, in either 8-bit

of 4-bit bus width.

Designers can either use parallel bus to achieve

high data transfer rate.

Bus Type

8080

6800

Width

Access

8-bit

4-bit

8-bit

4-bit

Read/Write

BM[1:0]

WR0

WR1

10

00

___ __

WR

___ __

RD

11

01

__

R/W

EN

D[7:4]

Data

–

Data

–

D[3:0]

Data

Data

Data

Data

* Connect unused control pins and data bus pins to VDD or VSS

Table 5: Host interfaces Choices

PARALLEL INTERFACE

The timing relationship between UC1608 internal

control signal RD, WR and their associated bus

actions are shown in the figure below.

The Display RAM read interface is implemented

as a two-stage pipe-line. This architecture

requires that, every time memory address is

modified, either in 8-bit mode or 4-bit mode, by

either Set CA, or Set PA command, a dummy

read cycle need to be performed before the

actual data can propagate through the pipe-line

and be read from data port D[7:0].

There is no pipeline in write interface of Display

RAM. Data is transferred directly from bus buffer

to internal RAM on the rising edges of write

pulses.

8-BIT & 4-BIT BUS OPERATION

UC1608 supports both 8-bit and 4-bit bus width.

The bus width is determined by pin BM[1].

4-bit bus operation exactly doubles the clock

cycles of 8-bit bus operation, MSB followed by

LSB, including the dummy read, which also

requires two clock cycles.

External

CD

___

WR

__

RD

D[7:0]

LLSB

DL

DL+K

CMSB

CLSB

Dummy DC

DC+1

MMSB

MLSB

Internal

Write

Read

Data

Latch

DL

DL+K

Dummy

DC

DC+1

DC+2

Column

Address

L

L+K L+K+1

C

C+1

C+2

C+3

M

Figure 5: 8 bit Parallel Interface & Related Internal Signals

(Revision 0.52 Preview)

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