W986416DH 查看數據表（PDF） - Winbond

零件编号

产品描述 (功能)

生产厂家

W986416DH

1M x 4 BANKS x 16 BITS SDRAM

Winbond 

W986416DH

Notes:

1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the devices.

2. All voltages are referenced to VSS.

3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of tCK

and tRC.

4. These parameters depend on the output loading conditions. Specified values are obtained with output open.

5. Power up Sequence

(1) Power up must be performed in the following sequence.

(2) Power must be applied to VCC and VCCQ (simultaneously) while all input signals are held in the “NOP” state. The CLK

signals must be started at the same time.

(3) After power-up a pause of at least 200 µseconds is required. It is required that DQM and CKE signals then be held

"high" (VCC levels) to ensure that the DQ output is impedance.

(4) All banks must be precharged.

(5) The Mode Register Set command must be asserted to initialize the Mode Register.

(6) A minimum of eight Auto Refresh dummy cycles is required to stabilize the internal circuitry of the device.

6. AC Testing Conditions

PARAMETER

Output Reference Level

Output Load

Input Signal Levels (VIH/VIL)

Transition Time (Rise and Fall) of Input Signal

Input Reference Level

CONDITIONS

1.4V

See diagram below

2.4V/0.4V

1 nS

1.4V

output

Z = 50 ohms

1.4 V

50 ohms

30pF

AC TEST LOAD

1. Transition times are measured between VIH and VIL.

2. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output

level.

3. These parameters account for the number of clock cycles and depend on the operating frequency of the clock,

as follows the number of clock cycles = specified value of timing/ clock period

(count fractions as whole number)

(1) tCH is the pulse width of CLK measured from the positive edge to the negative edge referenced to VIH (min.).

tCL is the pulse width of CLK measured from the negative edge to the positive edge referenced to VIL (max.).

- 17 -

Publication Release Date: April 11, 2002

Revision A4

Share Link: