White Electronic Designs
WMS512K8-XXX
TIMING WAVEFORM - READ CYCLE
ADDRESS
DATA I/O
tRC
tAA
tOH
PREVIOUS DATA VALID
DATA VALID
READ CYCLE 1 (CS# = OE# = VIL, WE# = VIH)
ADDRESS
CS#
OE#
DATA I/O
tRC
tAA
tACS
tCLZ
tCHZ
tOE
tOLZ
HIGH IMPEDANCE
tOHZ
DATA VALID
READ CYCLE 2 (WE# = VIH)
WRITE CYCLE - WE# CONTROLLED
ADDRESS
CS#
tAS
WE#
DATA I/O
tWC
tAW
tCW
tAH
tWHZ
tWP
tOW
tDW
tDH
DATA VALID
WRITE CYCLE 1, WE# CONTROLLED
WRITE CYCLE - CS# CONTROLLED
tWC
ADDRESS
tAW
tAS
tCW
tAH
CS#
WE#
DATA I/O
tWP
tDW
tDH
DATA VALID
WRITE CYCLE 2, CS# CONTROLLED
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October 2004
Rev. 10
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com