1205Z 查看數據表（PDF） - Intersil

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产品描述 (功能)

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1205Z

2-Wire™ RTC Real Time Clock/Calendar

Intersil 

X1205

Figure 10. Random Address Read Sequence

S

S

Signals from

the Master

t

a

Slave

r Address

Word

Address 1

Word

Address 0

t

a Slave

r Address

S

t

o

t

t

p

SDA Bus

Signals from

the Slave

11 011 11 0 00 000 00

A

A

C

C

K

K

11 011 1 11

A

A

C

C

K

K

Data

Figure 11. Sequential Read Sequence

S

Signals from

Slave

A

A

A

t

the Master

Address

C

K

C

K

C

K

o

p

SDA Bus

1

Signals from

the Slave

A

C

Data

K

(1)

Data

(2)

Data

(n-1)

Data

(n)

(n is any integer greater than 1)

16

FN8097.2

September 23, 2005

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