XRT72L52(2001) 查看數據表（PDF） - Exar Corporation

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XRT72L52
(Rev.:2001)

TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

Exar Corporation 

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PRELIMINARY

XRT72L52

TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

REV. P1.1.3

RX DS3 LAPD CONTROL REGISTER (ADDRESS = 0X18) ........................................................................ 215

RX DS3 LAPD STATUS REGISTER (ADDRESS = 0X19) .......................................................................... 215

TABLE 41: THE RELATIONSHIP BETWEEN RXLAPDTYPE[1:0] AND THE RESULTING LAPD MESSAGE TYPE AND

SIZE ...................................................................................................................................................... 216

Figure 86. Flow Chart depicting the Functionality of the LAPD Receiver .......................................... 217

4.3.4 The Receive Overhead Data Output Interface ...................................................................................... 217

Figure 87. A Simple Illustration of the Receive Overhead Output Interface block ............................. 218

TABLE 42: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT

INTERFACE BLOCK ................................................................................................................................ 219

Figure 88. Illustration of how to interface the Terminal Equipment to the Receive Overhead Data Output

Interface block (for Method 1). ............................................................................................................ 219

TABLE 43: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN RXOHCLK, (SINCE RXO-

HFRAME WAS LAST SAMPLED "HIGH") TO THE DS3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT

PIN ....................................................................................................................................................... 220

Figure 89. Illustration of the signals that are output via the Receive Overhead Output Interface (for Method

1). ........................................................................................................................................................ 222

TABLE 44: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT

INTERFACE BLOCK (METHOD 2) ............................................................................................................. 223

Figure 90. Illustration of how to interface the Terminal Equipment to the Receive Overhead Data Output

Interface block (for Method 2). ............................................................................................................ 224

TABLE 45: THE RELATIONSHIP BETWEEN THE NUMBER OF RXOHENABLE OUTPUT PULSES ((SINCE RXOHFRAME

WAS LAST SAMPLED "HIGH") TO THE DS3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT PIN

225

Figure 91. Illustration of the signals that are output via the Receive Overhead Data Output Interface block

(for Method 2). ..................................................................................................................................... 227

4.3.5 The Receive Payload Data Output Interface ......................................................................................... 227

Figure 92. A Simple illustration of the Receive Payload Data Output Interface block ........................ 228

TABLE 46: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE PAYLOAD DATA OUTPUT IN-

TERFACE BLOCK .................................................................................................................................... 229

Figure 93. Illustration of the XRT72L52 DS3/E3 Framer IC being interfaced to the Receive Terminal Equip-

ment (Serial Mode Operation) ............................................................................................................. 230

Figure 94. An Illustration of the behavior of the signals between the Receive Payload Data Output Interface

block of the XRT72L52 and the Terminal Equipment (Serial Mode Operation) .................................. 231

Figure 95. Illustration of the XRT72L52 DS3/E3 Framer IC being interfaced to the Receive Section of the

Terminal Equipment (Nibble-Mode Operation) ................................................................................... 232

Figure 96. An Illustration of the Behavior of the signals between the Receive Payload Data Output Interface

Block of the XRT72L52 and the Terminal Equipment (Nibble-Mode Operation). ............................... 233

4.3.6 Receive Section Interrupt Processing ................................................................................................... 233

BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ..................................................................... 234

RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) .................................................................... 234

RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) .................................................................... 235

RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ......................................................... 235

RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) .................................................................... 236

RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) .................................................................... 236

RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ......................................................... 236

RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) .................................................................... 237

RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) .................................................................... 237

RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ......................................................... 238

RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) .................................................................... 238

RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) .................................................................... 239

RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ......................................................... 239

RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) .................................................................... 239

RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) .................................................................... 240

RXDS3 STATUS REGISTER (ADDRESS = 0X11) ...................................................................................... 240

RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) .................................................................... 240

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