BA10358F/FV, BA10324AF/FV, BA2904SF/FV/FVM, BA2904F/FV/FVM
BA2902SF/FV/KN, BA2902F/FV/KN, BA3404F/FVM
●Circuit Diagram
VCC
VCC
Technical Note
-IN
-IN
VOUT +IN
+IN
VOUT
VEE
VEE
Fig. 119 Schematic Diagram
(BA10358/BA10324A/BA2904S/
BA2904/BA2902S/BA2902)
Fig. 120 Schematic Diagram
(BA3404)
●Test circuit1 NULL method
Parameter
VCC,VEE,EK,Vicm Unit:[V]
VF S1 S2 S3
BA10358 family
BA10324A family
BA2904 family
BA2902 family
BA3404 family
calculation
VCC VEE EK Vicm VCC VEE EK Vicm VCC VEE EK Vicm
Input Offset Voltage
VF1 ON ON OFF 5 0 -1.4 0 5~30 0 -1.4 0 15 -15 0 0
1
Input Offset Current
VF2 OFF OFF OFF 5 0 -1.4 0 5 0 -1.4 0 15 -15 0 0
2
Input Bias Current
VF3 OFF ON
OFF 5 0 -1.4 0 5 0 -1.4 0 15 -15 0 0
3
VF4 ON OFF
VF5
15 0 -1.4 0 15 0 -1.4 0 15 -15 10 0
Large Signal Voltage Gain
ON ON ON
4
VF6
15 0 -11.4 0 15 0 -11.4 0 15 -15 -10 0
Common-mode Rejection VF7
5 0 -1.4 0 5 0 -1.4 0 15 -15 0 -15
Ratio (Input common-mode
ON ON OFF
5
Voltage Range)
VF8
5 0 -1.4 3.5 5 0 -1.4 3.5 15 -15 0 13
Power Supply
Rejection Ratio
VF9
5 0 -1.4 0 5 0 -1.4 0 2 -2 0 0
ON ON OFF
6
VF10
30 0 -1.4 0 30 0 -1.4 0 15 -15 0 0
-Calculation-
1. Input Offset Voltage (Vio)
VF1
Vio
[V]
1+ Rf / Rs
2. Input Offset Current (Iio)
VF2 - VF1
Iio
[A]
Ri ×(1+ Rf / Rs)
3. Input Bias Current (Ib)
VF4 - VF3
Ib
[A]
2×Ri× (1+ Rf / Rs)
4. Large Signal Voltage Gain (Av)
Av 20 ×LogΔEK × (1+ Rf/Rs) [dB]
VF5 - VF6
5. Common-mode Rejection Ration (CMRR)
CMRR 20 ×LogΔVicm× (1+ Rf/Rs) [dB]
VF8 - VF7
C2
0.1[μF]
S1
Rs
Ri
50[Ω] 10[kΩ]
50[Ω] 10[kΩ]
Rs
Ri
Vicm
S2
VCC
DUT
VEE
Rf
50[kΩ]
EK
RK
500[kΩ]
RK 500[kΩ]
S3
C3
1000[pF]
RL
C1
0.1[μF]
+15[V]
NULL
-15[V]
V VF
Fig. 121 Test circuit1 (one channel only)
6. Power supply rejection ratio (PSRR)
PSRR 20 ×LogΔVcc × (1+ Rf/Rs) [dB]
VF10 - VF9
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2011.08 - Rev.B