ADP3410KRU 查看數據表（PDF） - Analog Devices

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ADP3410KRU

Dual MOSFET Driver with Bootstrapping

Analog Devices 

ADP3410

Pin Mnemonic

1

OVPSET

2

SD

3

GND

4

IN

5

DRVLSD

6

DLY

7

VCCGD

8

VCC

9

DRVL

10

PGND

11

SRMON

12

SW

13

DRVH

14

BST

PIN FUNCTION DESCRIPTIONS

Function

Overvoltage Shutdown Sense Input. Shutdown occurs when this pin is driven above the specified thresh-

old. It is a high-impedance comparator input, so an external resistor divider can be used to scale the

controlling voltage for OVP.

Shutdown. When high, this pin enables normal operation. When low, VCCGD, DRVH, and DRVL are

forced low and the supply current (ICCQ) is minimized as specified.

Signal Ground. The input signal and the capacitor at DLY should be closely referenced to this ground.

TTL-level input signal which has primary control of the drive outputs.

Synchronous Rectifier Enable. When low, this signal forces DRVL low. The propagation delay time is on

the order of that for the main input signal, so it can be used for real time modulation control of DRVL.

When DRVLSD is high, DRVL is enabled and controlled by IN.

Low-High-Transition Delay. A capacitor from this pin to ground programs the propagation delay

from turn-off of the lower FET to turn-on of the upper FET. The formula for the low-high-transition

delay is DLY = CDLY ¥ (1 ns/pF) + 20 ns. The rise time for turn-on of the upper FET is not included in

the formula.

VCC Good. This pin indicates the status of the undervoltage lockout. When VCC is high enough for the

device to exit UVLO mode, the VCCGD pin is pulled up to VCC with the specified low impedance. This

signal is capable of acting as a switched power rail for external circuitry, since it can source 10 mA and

sink 10 mA.

Input Supply. This pin should be bypassed to PGND with ~1 mF ceramic capacitor.

Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) FET.

Power Ground. Should be closely connected to the source of the lower FET.

Synchronous Rectifier Monitor. When DRVLSD is high, SRMON follows DRVL. When DRVLSD is

low, SRMON is high. TTL-type output.

This pin is connected to the buck switching node, close to the upper FET’s source. It is the floating return

for the upper FET drive signal. Also, it is used to monitor the switched voltage to prevent turn-on of the

lower FET until the voltage is below ~1 V. Thus, the high-low-transition delay is determined at this pin

according to operating conditions. This pin can be subjected to voltages as low as 2 V below PGND.

Buck Drive. Output drive for the upper (buck) FET.

Floating Bootstrap Supply for the upper FET. A capacitor connected between BST and SW pins holds

this bootstrapped voltage for the high-side FET as it is switched. The capacitor should be chosen between

0.1 mF and 1 mF.

PIN CONFIGURATION

OVPSET 1

14 BST

SD 2

13 DRVH

GND 3

12 SW

IN 4 ADP3410 11 SRMON

TOP VIEW

DRVLSD 5 (Not to Scale) 10 PGND

DLY 6

VCCGD 7

9 DRVL

8 VCC

–4–

REV. A

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