PULSE
GENERATOR 1
PULSE
GENERATOR 2
VDD
Ain Aout
Aout
DIS
Bout
Bin Bout
VDD
1 k*
1
SW
2
CL
1 k*
VSS
Test
ton HL
ton LH
toff HL
toff LH
Switch Position
1
2
2
1
* Metal film, ± 1%, 1/4 W or greater
CL = 15 pF, which includes test circuit capacitance.
Ain
Bin
3–STATE
DISABLE
Aout
Bout
50%
ton LH
ton LH
10%
toff LH
toff LH
VOH′ ton HL
90%
90%
VOH
10%
VOL
toff HL
toff LH
90% VOH′
VOH′
90% VOH
VDD
VSS
VDD
VSS
VDD
VSS
VOH
10% (VOH – VOL′)
VOL′VOL
VOH
10% (VOH – VOL′)
VOL′ VOL
SWITCH POSITION 2
SWITCH POSITION 1
VOL′ and VOH′ refer to the levels present as a result of the 1 k ohm load resistors.
Figure 5. 3–State Switching Time Test Circuit and Waveforms
MC14583B
6
MOTOROLA CMOS LOGIC DATA