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AD1981B

AC ’97 SoundMAX® Codec

Analog Devices 

AD1981B

VRAS

SPDIF

DSA[1,0]

AMAP

REVC[1,0]

IDC[1:0]

Variable Rate PCM Audio Support (Read-Only). This bit returns a 1 when Read To indicates that the variable rate

PCM audio is supported.

SPDIF Support (Read-Only). This bit returns a 1 when Read To indicates that the SPDIF transmitter is supported

(IEC958).

This bit is also used to validate that the SPDIF transmitter output is actually enabled. The SPDIF bit is allowed to be

set high only if the SPDIF pin (48) is pulled down at power-up, enabling the codec transmitter logic. If the SPDIF

pin is floating or pulled high at power-up, the transmitter logic is disabled; therefore, this bit returns a low, indicat-

ing that the SPDIF transmitter is not available. This bit must always be read back to verify that the SPDIF transmitter

is actually enabled.

DAC Slot Assignments (Read/Write) (Reset Default = 00).

00 DACs 1, 2 = 3 and 4.

01 DACs 1, 2 = 7 and 8.

10 DACs 1, 2 = 6 and 9.

11 Reserved.

Slot DAC Mappings Based on Codec ID (Read-Only). This bit returns a 1 when read to indicate that slot/DAC

mappings based on the codec ID are supported.

REVC[1,0] = 01 indicates codec is AC ’97 revision 2.2 compliant (Read-Only).

Indicates Codec Configuration (Read-Only).

00 = Primary.

01, 10, 11 = Secondary.

Extended Audio Status and Control Register (Index 2Ah)

Reg

No. Name

D15

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

2Ah Ext’d Audio Stat/Ctrl VFORCE X X X X SPCV X X X X SPSA1 SPSA0 X SPDIF X VRA 0000h

All registers not shown and bits containing an X are assumed to be reserved. The Extended Audio Status and Control register is a read/write register that provides

status and control of the extended audio features.

VRA

SPDIF

SPSA[1:0]

SPCV

VFORCE

Variable Rate Audio (Read/Write).

VRA = 0 sets fixed sample rate audio at 48 kHz (reset default).

VRA = 1 enables variable rate audio mode (enables sample rate registers and SLOTREQ signaling).

SPDIF Transmitter Subsystem Enable/Disable Bit (Read/Write).

SPDIF = 1 enables the SPDIF transmitter.

SPDIF = 0 disables the SPDIF transmitter (default).

This bit is also used to validate that the SPDIF transmitter output is actually enabled. The SPDIF bit is only allowed

to be set high if the SPDIF pin (48) is pulled down at power-up, enabling the codec transmitter logic. If the

SPDIF pin is floating or pulled high at power-up, the transmitter logic is disabled and this bit therefore returns a low,

indicating that the SPDIF transmitter is not available. This bit must always be read back to verify that the SPDIF

transmitter is actually enabled.

SPDIF Slot Assignment Bits (Read/Write). These bits control the SPDIF slot assignment and respective defaults,

depending on the codec ID configuration.

SPDIF Configuration Valid (Read-Only). Indicates the status of the SPDIF transmitter subsystem, enabling the

driver to determine if the currently programmed SPDIF configuration is supported. SPCV is always valid, independent

of the SPDIF enable bit status.

SPCV = 0 indicates current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is not valid (not supported).

SPCV = 1 indicates current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is valid (is supported).

Validity Force Bit (Reset Default = 0).

When asserted, this bit forces the SPDIF stream validity flag (Bit 28 within each SPDIF L/R subframe) to be

controlled by the V bit (D15) in Register 3Ah (SPDIF control register).

VFORCE = 0 and V = 0; the Validity bit is managed by the codec error detection logic.

VFORCE = 0 and V = 1; the Validity bit is forced high, indicating subframe data is invalid.

VFORCE = 1 and V = 0; the Validity bit is forced low, indicating subframe data is valid.

VFORCE = 1 and V = 1; the Validity bit is forced high, indicating subframe data is invalid.

–18–

REV. B

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