ADP34190091RMZR 查看數據表（PDF） - ON Semiconductor
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ADP34190091RMZR Datasheet PDF : 10 Pages
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ADP3419
When DRVLSD is low, the low-side driver stays low.
When DRVLSD is high, the low-side driver is enabled and
controlled by the driver signals, as previously described.
Low-Side Driver Timeout
In normal operation, the DRVH signal tracks the IN signal
and turns off the Q1 high-side switch with a few 10 ns delay
(tpdlDRVH) following the falling edge of the input signal.
When Q1 is turned off, DRVL is allowed to go high, Q2 turns
on, and the SW node voltage collapses to zero. But in a fault
condition such as a high-side Q1 switch drain-source short
circuit, the SW node cannot fall to zero, even when DRVH
goes low. The ADP3419 has a timer circuit to address this
scenario. Every time the IN goes low, a DRVL on-time delay
timer is triggered. If the SW node voltage does not trigger a
low-side turn-on, the DRVL on-time delay circuit does it
instead, when it times out with tSW(TO) delay. If Q1 is still
turned on, that is, its drain is shorted to the source, Q2 turns
on and creates a direct short circuit across the VDCIN voltage
rail. The crowbar action causes the fuse in the VDCIN current
path to open. The opening of the fuse saves the load (CPU)
from potential damage that the high-side switch short circuit
could have caused.
Crowbar Function
In addition to the internal low-side drive time-out circuit,
the ADP3419 includes a CROWBAR input pin to provide a
means for additional overvoltage protection. When
CROWBAR goes high, the ADP3419 turns off DRVH and
turns on DRVL. The crowbar logic overrides the overlap
protection circuit, the shutdown logic, the DRVLSD logic,
and the UVLO protection on DRVL. Thus, the crowbar
function maximizes the overvoltage protection coverage in
the application. The CROWBAR can be either driven by the
CLAMP pin of buck controllers, such as the ADP3422,
ADP3203, ADP3204, or ADP3205, or controlled by an
independent overvoltage monitoring circuit.
Table 1. ADP3419 Truth Table
CROWBAR UVLO SD DRVLSD IN DRVH DRVL
L
L
H
H
HH
L
L
L
H
H
L
L
H
L
L
H
L
HH
L
L
L
H
L
L
L
L
L
L
L
*
*
L
L
L
H
*
*
*
L
L
H
L
*
*
*
L
H
H
H
*
*
*
L
H
* = Don’t Care.
Application Information
Supply Capacitor Selection
For the supply input (VCC) of the ADP3419, a local
bypass capacitor is recommended to reduce the noise and to
supply some of the peak currents drawn. Use a 10 mF or
4.7 mF multilayer ceramic (MLC) capacitor. MLC
capacitors provide the best combination of low ESR and
small size, and can be obtained from the following vendors.
Table 2.
Vendor
Part Number
Web Address
Murata
GRM235Y5V106Z16 www.murata.com
Taiyo-Yuden EMK325F106ZF
www.t-yuden.com
Tokin
C23Y5V1C106ZP
www.tokin.com
Keep the ceramic capacitor as close as possible to the ADP3419.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
(CBST) and a Schottky diode (D1), as shown in Figure 16.
Selection of these components can be done after the
high-side MOSFET has been chosen. The bootstrap
capacitor must have a voltage rating that is able to handle at
least 5.0 V more than the maximum supply voltage. The
capacitance is determined by:
where:
CBST
+
QHSGATE
DVBST
(eq. 1)
QHSGATE is the total gate charge of the high-side MOSFET.
DVBST is the voltage droop allowed on the high-side
MOSFET drive.
For example, two IRF7811 MOSFETs in parallel have a
total gate charge of about 36 nC. For an allowed droop of
100 mV, the required bootstrap capacitance is 360 nF. A
good quality ceramic capacitor should be used, and derating
for the significant capacitance drop of MLCs at high
temperature must be applied. In this example, selection of
470 nF or even 1 mF would be recommended.
A Schottky diode is recommended for the bootstrap diode
due to its low forward drop, which maximizes the drive
available for the high-side MOSFET. The bootstrap diode
must also be able to handle at least 5.0 V more than the
maximum battery voltage. The average forward current can
be estimated by:
IF(AVG) + QHSGATE fMAX
(eq. 2)
where fMAX is the maximum switching frequency of the
controller.
Power and Thermal Considerations
The major power consumption of the ADP3419-based
driver circuit is from the dissipation of MOSFET gate
charge. It can be estimated as:
PMAX [ VCC (QHSGATE ) QLSGATE) fMAX (eq. 3)
where:
VCC is the supply voltage 5.0 V.
fMAX is the highest switching frequency.
QHSGATE and QLSGATE are the total gate charge of high-side
and low-side MOSFETs, respectively.
For example, the ADP3419 drives two IRF7821 high-side
MOSFETs and two IRF7832 low-side MOSFETs. According
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