AS5C512K8EC-15 查看數據表（PDF） - Austin Semiconductor

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AS5C512K8EC-15

512K x 8 SRAM HIGH SPEED SRAM with REVOLUTIONARY PINOUT

Austin Semiconductor 

Austin Semiconductor, Inc.

FUNCTIONAL BLOCK DIAGRAM

VCC

GND

SRAM

AS5C512K8

A0-A18

4,194,304-BIT

MEMORY ARRAY

1024 ROWS X

4096 COLUMNS

DQ8

DQ1

COLUMN DECODER

*On the low voltage Data Retention option.

TRUTH TABLE

MODE

STANDBY

READ

NOT SELECTED

WRITE

OE\ CE\ WE\

XH X

LLH

HLH

XL L

I/O

HIGH-Z

Q

HIGH-Z

D

POWER

STANDBY

ACTIVE

ACTIVE

ACTIVE

X = Don’t Care

CE\

OE\

WE\

*POWER

DOWN

PIN FUNCTIONS

A0 - A18 Address Inputs

WE\

Write Enable

CE\

Chip Enable

OE\

Output Enable

I/O0 - I/O7 Data Inputs/Outputs

VCC

Power

VSS

Ground

NC

No Connection

AS5C512K8

Rev. 7.0 05/08

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

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