HCPL-5300-500E 查看數據表（PDF） - Avago Technologies
零件编号
产品描述 (功能)
生产厂家
HCPL-5300-500E Datasheet PDF : 21 Pages
| |||
20
LED will remain off and no
common mode failure will occur.
Even if the LED momentarily
turns on, the 100 pF capacitor
from pins 6-5 will keep the output
from dipping below the threshold.
The recommended LED drive
circuit (Figure 15) provides about
10 V of margin between the
lowest optocoupler output voltage
and a 3 V IPM threshold during
a 15 kV/µs transient with
VCM = 1500 V. Additional margin
can be obtained by adding a diode
in parallel with the resistor, as
shown by the dashed line con-
nection in Figure 20, to clamp
the voltage across the LED
below VF(OFF).
Since the open collector drive
circuit, shown in Figure 21,
cannot keep the LED off during
a +dVcm/dt transient, it is
not desirable for applications
requiring ultra high CMRH
performance. Figure 22 is the AC
equivalent circuit for Figure 21
during common mode transients.
Essentially all the current flowing
through CLEDN during a +dVcm/dt
transient must be supplied by
the LED. CMRH failures can occur
at dV/dt rates where the current
through the LED and CLEDN
exceeds the input threshold.
Figure 23 is an alternative drive
circuit which does achieve ultra
high CMR performance by
shunting the LED in the off state.
IPM Dead Time and
Propagation Delay
Specifications
The HCPL-4506 series include
a Propagation Delay Difference
specification intended to help
designers minimize “dead time”
in their power inverter designs.
Dead time is the time period
during which both the high and
low side power transistors (Q1
and Q2 in Figure 24) are off. Any
overlap in Q1 and Q2 conduction
will result in large currents flow-
ing through the power devices
between the high and low voltage
motor rails.
To minimize dead time the
designer must consider the propa-
gation delay characteristics of the
optocoupler as well as the charac-
teristics of the IPM IGBT gate
drive circuit. Considering only the
delay characteristics of the opto-
coupler (the characteristics of the
IPM IGBT gate drive circuit can
be analyzed in the same way) it is
important to know the minimum
and maximum turn-on (tPHL) and
turn-off (tPLH) propagation delay
specifications, preferably over the
desired operating temperature
range.
The limiting case of zero dead
time occurs when the input to Q1
turns off at the same time that the
input to Q2 turns on. This case
determines the minimum delay
between LED1 turn-off and LED2
turn-on, which is related to the
worst case optocoupler propaga-
tion delay waveforms, as shown in
Figure 25. A minimum dead time
of zero is achieved in Figure 25
when the signal to turn on LED2
is delayed by (tPLH max - tPHL min)
from the LED1 turn off. Note that
the propagation delays used to
calculate PDD are taken at equal
temperatures since the opto-
couplers under consideration
are typically mounted in close
proximity to each other.
(Specifically, tPLH max and tPHL min
in the previous equation are not
the same as the tPLH max and
tPHL min, over the full operating
temperature range, specified in
the data sheet.) This delay is the
maximum value for the propaga-
tion delay difference specification
which is specified at 450 ns for
the HCPL-4506 series over an
operating temperature range of
-40°C to 100°C.
Delaying the LED signal by the
maximum propagation delay dif-
ference ensures that the minimum
dead time is zero, but it does not
tell a designer what the maximum
dead time will be. The maximum
dead time occurs in the highly
unlikely case where one opto-
coupler with the fastest tPLH and
another with the slowest tPHL
are in the same inverter leg. The
maximum dead time in this case
becomes the sum of the spread
in the tPLH and tPHL propagation
delays as shown in Figure 26.
The maximum dead time is also
equivalent to the difference
between the maximum and mini-
mum propagation delay difference
specifications. The maximum
dead time (due to the optocoup-
lers) for the HCPL-4506 series
is 600 ns (= 450 ns - (-150 ns) )
over an operating temperature
range of -40°C to 100°C.
Share Link: 