MC56F8323PB 查看數據表（PDF） - Motorola => Freescale
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MC56F8323PB Datasheet PDF : 124 Pages
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Table 2-2 56F8323 Signal and Package Information for the 64-Pin LQFP
Signal Name Pin No.
Type
State During
Reset
Signal Description
TRST
58
PHASEA0
52
(TA0)
(GPIOB7)
(oscillator_clock)
PHASEB0
51
(TA1)
(GPIOB6)
(sys_clk2x)
Schmitt
Input
Input, pulled Test Reset — As an input, a low signal on this pin provides a
high internally reset signal to the JTAG TAP controller. To ensure complete
hardware reset, TRST should be asserted whenever RESET
is asserted. The only exception occurs in a debugging
environment when a hardware device reset is required and
the EOnCE/JTAG module must not be reset. In this case,
assert RESET, but do not assert TRST.
To deactivate the internal pull-up resistor, set the JTAG bit in
the SIM_PUDR register.
Schmitt
Input
Input Phase A — Quadrature Decoder 0 PHASEA input
Schmitt
Input/
Output
TA0 — Timer A Channel 0
Schmitt
Input/
Output
Port B GPIO — This GPIO pin can be individually
programmed as an input or output pin.
Output
Clock Output - can be used to monitor the internal oscillator
clock signal (see Section 6.5.7 CLKO Select Register
(SIM_CLKOSR).
After reset, the default state is PHASEA0.
Schmitt
Input
Input Phase B — Quadrature Decoder 0 PHASEB input
Schmitt
Input/
Output
TA1 — Timer A Channel 1
Schmitt
Input/
Output
Port B GPIO — This GPIO pin can be individually
programmed as an input or output pin.
Output
Clock Output - can be used to monitor the internal sys_clk2x
signal (see Section 6.5.7 CLKO Select Register
(SIM_CLKOSR).
After reset, the default state is PHASEB0.
14
56F8323 Technical Data
MOTOROLA
Preliminary
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