ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
TDE
tsu2
tP4
tsu1
fCL
tw
tw
TDC
1
2
3
4
5
6
7
tP1
tP3
tP3
TDD
*
MSB
* Data output during this time will vary depending on TDC rate and TDE timing.
tsu8
8
9
tP2
10
11
tP2
LSB
PCM WORD REPEATED
Figure 2. Transmit Timing Diagram
tw
RCE
tsu4
tsu3
RDC
1
2
tsu5
RDD
DON’T
CARE
th
MSB
fCL
tw
tw
3
4
5
6
7
8
9
LSB
Figure 3. Receive Timing Diagram
10
11
DON’T
CARE
tw
MSI
tsu7
tsu6
tw
tw
CCI
1
2
3
4
5
6
7
8
9
10
11
Figure 4. MSI/CCI Timing Diagram
Page 13 of 26
www.lansdale.com
Issue A