OX16PCI954-TQC60-A1 查看數據表（PDF） - Oxford Semiconductor

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OX16PCI954-TQC60-A1

Integrated Quad UART and PCI interface

Oxford Semiconductor 

OXFORD SEMICONDUCTOR LTD.

OX16PCI954

Mode

00

01

10

Serial port pins

81, 78, 58, 53

83, 76, 60, 51

84, 75, 61, 50

86, 73, 67, 48

64

63

8-bit local bus

71

N/A

122

123

102

N/A

N/A

N/A

109

N/A

114-7

N/A

112

N/A

113

N/A

105-8

N/A

118-21

92-5

N/A

98-101

Dir1

11

N/A O

N/A

I

N/A

I

I

N/A

I

I

N/A O

N/A

I

O

O

O

O

See

O

32-bit O

Local

bus

O

O

O

O

Z

O

I/O

Name

Description

RTS[3:0]#

CTS[3:0]#

DSR[3:0]#

Active-low modem request-to-send output. If automated

RTS# flow control is enabled, the RTS# pin is deasserted

and reasserted whenever the receiver FIFO reaches or falls

below the programmed thresholds, respectively.

Active-low modem clear-to-send input. If automated CTS#

flow control is enabled, upon deassertion of the CTS# pin,

the transmitter will complete the current character and enter

the idle mode until the CTS# pin is reasserted. Note: flow

control characters are transmitted regardless of the state of

the CTS# pin.

Active-low modem data-set-ready input. If automated DSR#

flow control is enabled, upon deassertion of the DSR# pin,

the transmitter will complete the current character and enter

the idle mode until the DSR# pin is reasserted. Note: flow

control characters are transmitted regardless of the state of

the DSR# pin

Rx_Clk_In[3:0]

RI[3:0]#

External receiver clock for isochronous applications. The

Rx_Clk_In is selected when CKS[1:0] = ‘01’.

Active-low modem Ring-Indicator input

Tx_Clk_In[3:0]

XTLO

XTLI

External transmitter clock. This clock can be used by the

transmitter (and indirectly by the receiver) when CKS[6]=’1’.

Crystal oscillator output

Crystal oscillator input or external clock pin. Maximum

frequency 60MHz

UART_Clk_Out

LBRST

LBRST#

LBDOUT

LBCLK

LBCS[3:0]#

Buffered crystal output. This clock can drive external UARTs

connected to the local bus. Can be enabled / disabled by

software.

Local bus active-high reset

Local bus active-low reset

Local bus data out enable. This pin can be used by external

transceivers; it is high when LBD[7:0] are in output mode and

low when they are in input mode.

Buffered PCI clock. Can be enabled / disabled by software

Local bus active-low Chip-Select (Intel mode)

LBDS[3:0]#

LBWR#

Local bus active-low Data-Strobe (Motorola mode)

Local Bus active-low write-strobe (Intel mode)

LBRDWR#

LBRD#

Local Bus Read-not-Write control (Motorola mode)

Local Bus active-low read-strobe (Intel mode)

Hi-Z

LBA[7:0]

LBD[7:0]

Permanent high impedance (Motorola mode)

Local bus address signals

Local bus data signals

DS-0029 Jul 05

External—Free Release

Page 10

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