ST7565P 查看數據表（PDF） - Unspecified

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ST7565P

65 x 132 Dot Matrix LCD Controller/Driver

Unspecified 

ST7565P

Item

Address hold time

Address setup time

System cycle time

Write L pulse width

Write H pulse width

Read L pulse width

Read H pulse width

Write Data setup time

Write Address hold time

Read access time

Read Output disable time

Table 25

Signal

A0

WR

RD

D0 to D7

Symbol

tAH8

tAW8

tCYC8

tCCLW

tCCHW

tCCLR

tCCHR

tDS8

tDH8

tACC8

tOH8

Condition

CL = 100 pF

CL = 100 pF

(VDD = 2.7V, Ta = –30 to 85°C)

Rating

Min.

Max.

Units

0

—

0

—

400

—

220

—

180

—

220

—

ns

180

—

40

—

0

—

—

140

10

100

Item

Address hold time

Address setup time

System cycle time

Write L pulse width

Write H pulse width

Read L pulse width

Read H pulse width

Write Data setup time

Write Address hold time

Read access time

Read Output disable time

Table 26

Signal

A0

WR

RD

D0 to D7

Symbol

tAH8

tAW8

tCYC8

tCCLW

tCCHW

tCCLR

tCCHR

tDS8

tDH8

tACC8

tOH8

Condition

CL = 100 pF

CL = 100 pF

(VDD = 1.8V, Ta = –30 to 85°C)

Rating

Min.

Max.

Units

0

—

0

—

640

—

360

—

280

—

360

—

ns

280

80

—

0

—

—

240

10

200

*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,

(tr +tf) ≦ (tCYC8 – tCCLW – tCCHW) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR) are specified.

*2 All timing is specified using 20% and 80% of VDD as the reference.

*3 tCCLW and tCCLR are specified as the overlap between /CS1 being “L” (CS2 = “H”) and /WR and /RD being at the “L” level.

Ver 2.1b

62/71

2009/09/14

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