ST7565P 查看數據表（PDF） - Unspecified
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ST7565P Datasheet PDF : 71 Pages
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ST7565P
Item
Address hold time
Address setup time
System cycle time
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
WRITE Data setup time
WRITE Address hold time
READ access time
READ Output disable time
Table 28
Signal
A0
E
D0 to D7
Symbol
tAH6
tAW6
tCYC6
tEWLW
tEWHW
tEWLR
tEWHR
tDS6
tDH6
tACC6
tOH6
Condition
CL = 100 pF
CL = 100 pF
(VDD = 2.7V, Ta = –30 to 85°C)
Rating
Min.
Max.
Units
0
—
0
—
400
—
220
—
180
—
220
—
ns
180
—
40
—
0
—
—
140
10
100
Item
Address hold time
Address setup time
System cycle time
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
WRITE Data setup time
WRITE Address hold time
READ access time
READ Output disable time
Table 29
Signal
A0
E
D0 to D7
Symbol
tAH6
tAW6
tCYC6
tEWLW
tEWHW
tEWLR
tEWHR
tDS6
tDH6
tACC6
tOH6
Condition
CL = 100 pF
CL = 100 pF
(VDD = 1.8V, Ta = –30 to 85°C)
Rating
Min.
Max.
Units
0
—
0
—
640
—
360
—
280
—
360
—
ns
280
—
80
—
0
—
—
240
10
200
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr +tf) ≦ (tCYC6 – tEWLW – tEWHW) for (tr + tf) ≦ (tCYC6 – tEWLR – tEWHR) are specified.
*2 All timing is specified using 20% and 80% of VDD as the reference.
*3 tEWLW and tEWLR are specified as the overlap between CS1 being “L” (CS2 = “H”) and E.
Ver 2.1b
64/71
2009/09/14
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