KB3910 查看數據表（PDF） - Unspecified

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KB3910

Keyboard Controller

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KB3920 Keyboard Controller Datasheet

4.16.4 SFR Descriptions

(Direct Addressing 80h~FFh)

Addr

Register Register Full Name

Abbreviation Bit Attr Description

Def

Port 0 IE

80h

P0IE

00h

7 – 0 R/W P0 Interrupt Enable Register

Stack Pointer

81h

SP

07h

7 – 0 R/W Stack Pointer

DPTR Low Byte

82h

DPL

00h

7 – 0 R/W DPTR low byte

DPTR High Byte

83h

DPH

00h

7 – 0 R/W DPTR high byte

84h~85h

NA Reserved

00h

Processor Control Register 2

7

R/W Enable level trigger interrupt (KB3920 should set to 0)

6

R/W TTST, Timer 0/1 test mode, let timer 12 times faster.

5

R/W Reserved

4

R/W Enable external space write.

86h

PCON2

00h

Next Interrupt Coming Flag.

The same extended interrupt coming during ISR before IRET.

3

R/W After exit ISR with IRET instruction, the 8051 will re-enter the ISR

again if the flag is 1. Write 0 to clear the flag and prevent from 8051

re-entering the interrupt again after exit ISR.

2~1 NA Reserved

0

R/W Enable idle loop no fetching instruction

Processor Control Register

7~6 R/W Reserved

5

R/W

IVHB, Interrupt vector highest bit. Let interrupt vector to be 00xxh or

80xxh, including standard and extended interrupt.

4

R/W Reserved

3

R/W GF1, general purposes flag.

87h

PCON

2

R/W GF0, general purposes flag.

00h

Power Down Mode

1

WO

Stop all 8051 clock, including all peripherals (timer, interrupt, serial

port). An external Async. Wake-up event can reset the latch of 8051

gated clock. Write 1 to enter Power Down.

IDLE Mode.

0

WO

Set 1 to stop processor fetching instructions. But the clock will not

stop. Peripheral interrupt events will let processor exit IDLE mode.

Write 1 to enter IDLE.

88h

TCON Timer/Counter Control Register

00h

7 R/WC TF1 Timer 1 overflow flag.

6

R/W TR1 Timer 1 run control bit.

5 R/WC TF0 Timer 0 overflow flag.

Copyright©2006, ENE Technology Inc.

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