MACH111SP-18YI/1 查看數據表（PDF） - Lattice Semiconductor
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MACH111SP-18YI/1 Datasheet PDF : 48 Pages
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MACH231 AND MACH231SP
SWITCHING CHARACTERISTICS OVER OPERATING RANGES 1
Parameter
Symbol
Parameter Description
-6
-7
-10
-12
-14
-15
-18
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
tPD
Input, I/O, or Feedback to Combinatorial Output
6
7.5
10
12
14
15
18 ns
tS
Setup Time from Input, I/O, or Feedback D-type 5
to Clock
T-type 6
5.5
6.5
6.5
7.5
7
8
8.5
10
12
ns
10
11
13.5
ns
tH
Register Data Hold Time
0
0
0
0
0
0
0
ns
tCO
Clock to Output
4
5
6.5
8
10
10
12 ns
tWL
Clock Width
tWH
LOW 2.5
3
4
6
6
6
7.5
ns
HIGH 2.5
3
4
6
6
6
7.5
ns
External
D-type 111
95
Feedback
1/(tS + tCO)
T-type
100
87
77
66.7
54
50
42
MHz
72
62.5
50
47.6
39
MHz
fMAX
Maximum
D-type 166
Frequency Internal Feedback (fCNT)
133
100
83.3
69
66.6
55.6
MHz
T-type 150
125
91
76.9
62.5
62.5
51.3
MHz
No
Feedback
1/(tWL + tWH)
200
167
125
83.3
83.3
83.3
66.7
MHz
tSL
Setup Time from Input, I/O, or Feedback to Gate 5
5.5
6.5
7
8.5
10
12
ns
tHL
Latch Data Hold Time
0
0
0
0
0
0
0
ns
tGO
Gate to Output
5
6
7.5
8.5
11
11
13.5 ns
tGWL
Gate Width LOW
2
3
4
6
6
6
7.5
ns
tPDL
Input, I/O, or Feedback to Output Through
Transparent Input or Output Latch
9
9.5
14
14.5
17
17
20.5 ns
tSIR
Input Register Setup Time
1.5
2
2
2
2
2
2.5
ns
tHIR
Input Register Hold Time
1.5
2
2.5
2.5
2.5
2.5
3.5
ns
tICO
Input Register Clock to Combinatorial Output
10
11
15.5
16
18
18
22 ns
tICS
Input Register Clock to output Register D-type 8
Setup
T-type 9
9
11
12
14.5
15
18
ns
10
12
13
16
16
19.5
ns
tWICL
tWICH
fMAXIR
tSIL
tHIL
tIGO
tIGOL
Input Register
LOW
Clock Width
HIGH
Maximum Input Register Frequency
Input Latch Setup Time
Input Latch Hold Time
Input Latch Gate to Combinatorial Output
Input Latch Gate to Output Through Transparent
Output Latch
2.5
3
4
6
6
6
7.5
ns
2.5
3
4
6
6
6
7.5
ns
200
167
125
83.3
83.3
83.3
66.7
MHz
1.5
2
2
2.5
2.5
2.5
2.5
ns
1.5
2
2.5
3
3
3
3.5
ns
11
12
17
17
20
20
24 ns
13
14
18
19.5
22
22
26.5 ns
tSLL
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate
7
7.5
10
10.5
11
12
14.5
ns
tIGS
Input Latch Gate to Output Latch Setup
9
10
11
13.5
16
16
19.5
ns
MACH 1 & 2 Families
31
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