MACH231SP-12VI/1 查看數據表（PDF） - Lattice Semiconductor

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MACH231SP-12VI/1

High-Performance EE CMOS Programmable Logic

Lattice Semiconductor 

100-PIN PQFP CONNECTION DIAGRAM (MACH221SP-7/10/12/15)

Top View

100-Pin PQFP

Block A

Block H

GND

1

GND

2

TDI

3

I7

4

N/C

5

I/O6

6

N/C

7

I/O7

8

I/O8

9

I/O9

10

I/O10

11

I/O11

12

IO/CLK0

13

VCC

14

VCC

15

GND

16

GND

17

I1/CLK1

18

I/O12

19

I/O13

20

I/O14

21

I/O15

22

I/O16

23

N/C

24

I/O17

25

I2

26

N/C

27

TCK

28

GND

29

GND

30

80

GND

79

GND

78

TDO

77

N/C

76

I6

75

I/O41

74

N/C

73

I/O40

72

I/O39

71

I/O38

70

I/O37

69

I/O36

68

I5/CLK3

67

GND

66

GND

65

VCC

64

VCC

63

I4/CLK2

62

I/O35

61

I/O34

60

I/O33

59

I/O32

58

I/O31

57

N/C

56

I/O30

55

N/C

54

I3

53

TMS

52

GND

51

GND

PIN DESIGNATIONS

I/CLK = Input or Clock

GND = Ground

I

= Input

I/O = Input/Output

VCC = Supply Voltage

Block D

Block E

TDI = Test Data In

TCK = Test Clock

TMS = Test Mode Select

TDO = Test Data Out

MACH 1 & 2 Families

14051K-026

43

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