MACH111SP-14JC/1 查看數據表（PDF） - Lattice Semiconductor

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MACH111SP-14JC/1

High-Performance EE CMOS Programmable Logic

Lattice Semiconductor 

100-PIN PQFP CONNECTION DIAGRAM (MACH231SP-10/12/15)

Top View

100-Pin PQFP

Block A

Block H

GND

1

GND

2

TDI

3

I5

4

I/O8

5

I/O9

6

I/O10

7

I/O11

8

I/O12

9

I/O13

10

I/O14

11

I/O15

12

IO/CLK0

13

VCC

14

VCC

15

GND

16

GND

17

I1/CLK1

18

I/O16

19

I/O17

20

I/O18

21

I/O19

22

I/O20

23

I/O21

24

I/O22

25

I/O23

26

N/C

27

TCK

28

GND

29

GND

30

80

GND

79

GND

78

TDO

77

N/C

76

I/O55

75

I/O54

74

I/O53

73

I/O52

72

I/O51

71

I/O50

70

I/O49

69

I/O48

68

I4/CLK3

67

GND

66

GND

65

VCC

64

VCC

63

I3/CLK2

62

I/O47

61

I/O46

60

I/O45

59

I/O44

58

I/O43

57

I/O42

56

I/O41

55

I/O40

54

I2

53

TMS

52

GND

51

GND

PIN DESIGNATIONS

I/CLK = Input or Clock

GND = Ground

I

= Input

I/O = Input/Output

VCC = Supply Voltage

Block D

Block E

TDI = Test Data In

TCK = Test Clock

TMS = Test Mode Select

TDO = Test Data Out

MACH 1 & 2 Families

14051K-028

45

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