SPT7610 查看數據表（PDF） - Signal Processing Technologies
零件编号
产品描述 (功能)
生产厂家
SPT7610 Datasheet PDF : 10 Pages
| |||
Figure 1 – Timing Diagram
1 nsec
N+1
N
VIN
N+2
N+3
N+4
CLK (1 GHz)
tdrA
DRA
todA
DRA
tdrB
Data Bank A
N-4
N-2
N
DOADRA Delay
(todrA)
OutputA Skew
(toskA)
DRB
todB
DRB
Data Bank B N-5
N-3
N-1
OutputB Skew
(toskB)
DOB-DRB Delay
(todrB)
Figure 2 – Test Mode Timing Diagram
POWER FIRST
ON RISING EDGE
1
7
8
9
2
6
VIN
3
4
5
10
11
CLK IN
TEST
LOGIC LOW
ADC (Normal Operation)
DRA
tdr
tsu
TEST MODE
ADC (Normal Operation)
NDRA
tod
OUTPUT
BANK A
INVALID DATA
INVALID DATA
1
(DA0-6)
DRB
tdr
NDRB
OUTPUT
BANK B
(DB0-6)
INVALID DATA
tod
INVALID DATA
Bank A Test Pattern 1:
- Even Bits = Hi
- Odd Bits = Low
Bank A Test Pattern 2:
- Even Bits = Low
- Odd Bits = Hi
7
9
Bank B Test Pattern 1:
Bank B Test Pattern 2:
2
- Even Bits = Hi
- Even Bits = Low
8
- Odd Bits = Low
- Odd Bits = Hi
SPT
5
SPT7610
12/19/00
Share Link: 