MB40C328PFV 查看數據表（PDF） - Fujitsu

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MB40C328PFV

8-bit 100 MSPS A/D Converter

Fujitsu 

MB40C328

s BLOCK DIAGRAM

CKSEL DSEL VINA

CLKOA

Mode

setting

CLKA

CLK

CLK

select

Timing

circuit

A ch

CLKB

B ch

AVDD

Timing

circuit

RESET

CE

CLKOB

AVDD

DVDD

VREFT

AVDD

VRT

FF

VR3

VR2

VR1

FF

A output

buffer

DA0 to DA7

B output

buffer

DB0 to DB7

VRB

AVSS

AVSS

DVSS

OE VREFB

4

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