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MDLS16265D-03 查看數據表(PDF) - Unspecified

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MDLS16265D-03 Datasheet PDF : 13 Pages
First Prev 11 12 13
VL-FS-MDLS16265D-03 REV. A
(MDLS16265D-LV-G)
DEC/2003
PAGE 12 OF 13
5.3 Timing Diagram of VDD Against V0.
Power on sequence shall meet the requirement of Figure 4, the timing diagram of VDD against V0.
VDD
95%
LOGIC SUPPLY
VOLTAGE
0V
V0
50ms(typical)
0V
LCD SUPPLY
VOLTAGE
Figure 4: Timing Diagram of VDD Against V0.

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