GS71116AGU-12 查看數據表（PDF） - Unspecified
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GS71116AGU-12 Datasheet PDF : 16 Pages
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Block Diagram
GS71116ATP/J/U
Truth Table
CE OE
H
X
L
L
L
X
L
H
L
X
Note:
X: “H” or “L”
A0
Row
Decoder
Address
Input
Buffer
A15
CE
WE
OE
Control
UB _____
Memory Array
Column
Decoder
I/O Buffer
DQ1 DQ16
WE
LB
UB
X
X
X
L
L
H
L
H
H
L
L
L
L
L
H
H
L
H
X
X
X
H
H
DQ1 to DQ8
Not Selected
Read
Read
High Z
Write
Write
Not Write, High Z
High Z
High Z
DQ9 to DQ16
Not Selected
Read
High Z
Read
Write
Not Write, High Z
Write
High Z
High Z
VDD Current
ISB1, ISB2
IDD
Rev: 1.07 12/2004
3/16
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
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