TS912IYDT(2012) 查看數據表（PDF） - STMicroelectronics
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TS912IYDT Datasheet PDF : 21 Pages
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TS912, TS912A, TS912B
Electrical characteristics
Table 4.
VCC+ = 5 V, VCC- = 0 V, RL, CL connected to VCC/2, Tamb = 25 °C
(unless otherwise specified)
Symbol
Parameter
Min. Typ. Max.
Vio
ΔVio
Iio
Iib
ICC
CMR
SVR
Avd
VOH
VOL
Io
GBP
SR+
SR-
Input offset voltage (Vic = Vo = VCC/2)
TS912
TS912A
TS912B
Tmin ≤ Tamb ≤ Tmax
TS912
TS912A
TS912B
Input offset voltage drift
Input offset current(1)
Tmin ≤ Tamb ≤ Tmax
Input bias current(1)
Tmin ≤ Tamb ≤ Tmax
Supply current (per amplifier, AVCL = 1, no load)
Tmin ≤ Tamb ≤ Tmax
Common mode rejection ratio
Vic = 1.5 to 3.5 V, Vo = 2.5 V
Supply voltage rejection ratio (VCC+ = 3 to 5 V, Vo = VCC/2)
Large signal voltage gain (RL = 10 kΩ, Vo = 1.5 V to 3.5 V)
Tmin ≤ Tamb ≤ Tmax
High level output voltage (Vid = 1 V)
RL = 100 kΩ
RL = 10 kΩ
RL = 600 Ω
RL = 100 Ω
Tmin ≤ Tamb ≤ Tmax
RL = 10 kΩ
RL = 600 Ω
Low level output voltage (Vid = -1 V)
RL = 100 kΩ
RL = 10 kΩ
RL = 600 Ω
RL = 100 Ω
Tmin ≤ Tamb ≤ Tmax
RL = 10 kΩ
RL = 600 Ω
Output short-circuit current (Vid = ±1 V)
Source (Vo = VCC-)
Sink (Vo = VCC+)
Gain bandwidth product
(AVCL = 100, RL = 10 kΩ, CL = 100 pF, f = 100 kHz)
Slew rate (AVCL = 1, RL = 10 kΩ, CL = 100 pF, Vi = 1 V to 4 V)
Slew rate (AVCL = 1, RL = 10 kΩ, CL = 100 pF, Vi = 1 V to 4 V)
10
5
2
12
7
3
5
1
100
200
1
150
300
230 350
450
60 85
55 80
10 40
7
4.95
4.9 4.95
4.25 4.55
3.7
4.8
4.1
50
40 100
350 500
1400
150
750
45 65
45 65
1
0.8
0.6
Unit
mV
μV/°C
pA
pA
μA
dB
dB
V/mV
V
mV
mA
MHz
V/μs
V/μs
Doc ID 2325 Rev 7
7/21
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