TS912IYDT(2012) 查看數據表（PDF） - STMicroelectronics

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TS912IYDT
(Rev.:2012)

Rail-to-rail CMOS dual operational amplifier

STMicroelectronics 

TS912, TS912A, TS912B

Electrical characteristics

Table 5.

VCC+ = 10 V, VCC- = 0 V, RL, CL connected to VCC/2, Tamb = 25 °C

(unless otherwise specified)

Symbol

Parameter

Min. Typ.

Vio

ΔVio

Iio

Iib

ICC

CMR

SVR

Avd

VOH

VOL

Io

GBP

Input offset voltage (Vic = Vo = VCC/2)

TS912

TS912A

TS912B

Tmin ≤ Tamb ≤ Tmax

TS912

TS912A

TS912B

Input offset voltage drift

Input offset current(1)

Tmin ≤ Tamb ≤ Tmax

Input bias current(1)

Tmin ≤ Tamb ≤ Tmax

Supply current (per amplifier, AVCL = 1, no load)

Tmin ≤ Tamb ≤ Tmax

Common mode rejection ratio

Vic = 3 to 7 V, Vo = 5 V

Vic = 0 to 10 V, Vo = 5 V

Supply voltage rejection ratio (VCC+ = 5 to 10 V, Vo = VCC/2)

Large signal voltage gain (RL = 10 kΩ, Vo = 2.5 V to 7.5 V)

Tmin ≤ Tamb ≤ Tmax

High level output voltage (Vid = 1V)

RL = 100 kΩ

RL = 10 kΩ

RL = 600 Ω

RL = 100 Ω

Tmin ≤ Tamb ≤ Tmax

RL = 10 kΩ

RL = 600 Ω

Low level output voltage (Vid = -1 V)

RL = 100 kΩ

RL = 10 kΩ

RL = 600 Ω

RL = 100 Ω

Tmin ≤ Tamb ≤ Tmax

RL = 10 kΩ

RL = 600 Ω

Output short-circuit current (Vid = ±1 V)

Source (Vo = VCC-)

Sink (Vo = VCC+)

Gain bandwidth product

(AVCL = 100, RL = 10 kΩ, CL = 100 pF, f = 100 kHz)

5

1

1

400

60

90

50

75

60

90

15

50

10

9.95

9.85 9.95

9

9.35

7.8

9.8

8.8

50

650

2300

45

65

50

75

1.4

Max.

10

5

2

12

7

3

100

200

150

300

600

700

50

150

800

150

900

Unit

mV

μV/°C

pA

pA

μA

dB

dB

V/mV

V

mV

mA

MHz

Doc ID 2325 Rev 7

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