IS42R16320D-7BL 查看數據表（PDF） - Integrated Silicon Solution
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IS42R16320D-7BL Datasheet PDF : 66 Pages
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IS42/45R86400D/16320D/32160D, IS42/45S86400D/16320D/32160D
AC ELECTRICAL CHARACTERISTICS (1,2,3)
-5 -6 -7
Symbol Parameter
tck3
Clock Cycle Time
tck2
CAS Latency = 3
CAS Latency = 2
tac3
Access Time From CLK
tac2
CAS Latency = 3
CAS Latency = 2
Min. Max.
5—
10 —
— 5.0
—6
Min. Max.
6—
10 —
— 5.4
—6
Min. Max.
7—
7.5 —
— 5.4
— 5.4
Units
ns
ns
ns
ns
tch
CLK HIGH Level Width
2—
2.5 —
2.5 —
ns
tcl
CLK LOW Level Width
toh3
Output Data Hold Time
toh2
2—
CAS Latency = 3 2.5 —
CAS Latency = 2 2.5 —
2.5 —
2.5 —
ns
2.7 —
2.7 —
ns
2.7 —
2.7 —
ns
tlz
Output LOW Impedance Time
0—
0—
0—
ns
thz3
Output HIGH Impedance Time
—5
— 5.4
— 5.4
ns
thz2
—6
—6
— 5.4
ns
tds
Input Data Setup Time(2)
1.8 —
1.5 —
1.5 —
ns
tdh
Input Data Hold Time(2)
0.8 —
0.8 —
0.8 —
ns
tas
Address Setup Time(2)
1.5 —
1.5 —
1.5 —
ns
tah
Address Hold Time(2)
0.8 —
0.8 —
0.8 —
ns
tcks
CKE Setup Time(2)
1.5 —
1.5 —
1.5 —
ns
tckh
CKE Hold Time(2)
tcms
Command Setup Time (CS, RAS, CAS, WE, DQM)(2)
tcmh
Command Hold Time (CS, RAS, CAS, WE, DQM)(2)
0.8 —
1.5 —
0.8 —
0.8 —
0.8 —
ns
1.5 —
1.5 —
ns
0.8 —
0.8 —
ns
trc
Command Period (REF to REF / ACT to ACT)
55 —
60 —
60 —
ns
tras
Command Period (ACT to PRE)
38 100K
42 100K
37 100K
ns
trp
Command Period (PRE to ACT)
15 —
18 —
15 —
ns
trcd Active Command To Read / Write Command Delay Time
15 —
18 —
15 —
ns
trrd Command Period (ACT [0] to ACT[1])
10 —
12 —
14 —
ns
tdpl
Input Data To Precharge
Command Delay time
10 —
12 —
14 —
ns
tdal
Input Data To Active / Refresh
Command Delay time (During Auto-Precharge)
25 —
30 —
29 —
ns
tmrd Mode Register Program Time
10 —
12 —
14 —
ns
tdde
Power Down Exit Setup Time
5—
6—
7—
ns
txsr
Self-Refresh Exit Time
60 —
70 —
67 —
ns
tt
Transition Time
0.3 1.2
0.3 1.2
0.3 1.2
ns
tref
Refresh Cycle Time (8192) Ta ≤ 70oC Com, Ind, A1, A2 — 64
— 64
— 64
ms
Ta ≤ 85oC Ind, A1, A2 — 64
— 64
— 64
ms
Ta > 85oC A2 — —
——
— 16
ms
Notes:
1. The power-on sequence must be executed before starting memory operation.
2. Measured with tt = 1 ns. If clock rising time is longer than 1ns, (tt /2 - 0.5) ns should be added to the parameter.
3. The reference level is 1.4V when measuring input signal timing. Rise and fall times are measured between Vih(min.) and Vil
(max).
Integrated Silicon Solution, Inc. — www.issi.com
19
Rev. A
08/29/2012
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