IS42R16320D-7BL 查看數據表（PDF） - Integrated Silicon Solution

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IS42R16320D-7BL

DRAM 512M (32Mx16) 143MHz SDR SDRAM, 3.3V

Integrated Silicon Solution 

IS42/45R86400D/16320D/32160D, IS42/45S86400D/16320D/32160D

FUNCTIONAL DESCRIPTION

The 512Mb SDRAMs are quad-bank DRAMs which oper-

ate at 3.3V or 2.5V and include a synchronous interface

(all signals are registered on the positive edge of the clock

signal, CLK).

Read and write accesses to the SDRAM are burst oriented;

accesses start at a selected location and continue for

a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an AC-

TIVE command which is then followed by a READ or WRITE

command. The address bits registered coincident with the

ACTIVE command are used to select the bank and row to

be accessed (BA0 and BA1 select the bank, A0-A12 select the

row).The address bits A0-An; registered coincident with the

READ or WRITE command are used to select the starting

column location for the burst access.

Prior to normal operation, the SDRAM must be initial-

ized. The following sections provide detailed information

covering device initialization, register definition, command

descriptions and device operation.

Initialization

SDRAMs must be powered up and initialized in a

predefined manner.

The 512Mb SDRAM is initialized after the power is applied

to Vdd and Vddq (simultaneously) and the clock is stable

with DQM High and CKE High.

A 100µs delay is required prior to issuing any command

other than a COMMAND INHIBIT or a NOP. The COMMAND

INHIBIT or NOP may be applied during the 100us period and

should continue at least through the end of the period.

With at least one COMMAND INHIBIT or NOP command

having been applied, a PRECHARGE command should

be applied once the 100µs delay has been satisfied. All

banks must be precharged. This will leave all banks in an

idle state after which at least two AUTO REFRESH cycles

must be performed.  After the AUTO REFRESH cycles are

complete, the SDRAM is then ready for mode register

programming.

The mode register should be loaded prior to applying

any operational command because it will power up in an

unknown state.

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Integrated Silicon Solution, Inc. — www.issi.com

Rev. A

08/29/2012

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