IS42R16320D-7BL 查看數據表（PDF） - Integrated Silicon Solution

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IS42R16320D-7BL

DRAM 512M (32Mx16) 143MHz SDR SDRAM, 3.3V

Integrated Silicon Solution 

IS42/45R86400D/16320D/32160D, IS42/45S86400D/16320D/32160D

CLOCK SUSPEND

Clock suspend mode occurs when a column access/burst

is in progress and CKE is registered LOW. In the clock

suspend mode, the internal clock is deactivated, “freezing”

the synchronous logic.

For each positive clock edge on which CKE is sampled

LOW, the next internal positive clock edge is suspended.

Any command or data present on the input pins at the time

Clock Suspend During WRITE Burst

T0

T1

T2

CLK

of a suspended internal clock edge is ignored; any data

present on the DQ pins remains driven; and burst counters

are not incremented, as long as the clock is suspended.

(See following examples.)

Clock suspend mode is exited by registering CKE HIGH;

the internal clock and related operation will resume on the

subsequent positive clock edge.

T3

T4

T5

CKE

INTERNAL

CLOCK

COMMAND NOP

WRITE

NOP

NOP

ADDRESS

BANK a,

COL n

DQ

DIN n

DIN n+1

DIN n+2

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Clock Suspend During READ Burst

T0

T1

T2

T3

T4

T5

T6

CLK

CKE

INTERNAL

CLOCK

COMMAND READ

ADDRESS

BANK a,

COL n

DQ

NOP

NOP

DOUT n

Integrated Silicon Solution, Inc. — www.issi.com

Rev. A

08/29/2012

NOP

NOP

NOP

DOUT n+1

DOUT n+2

DOUT n+3

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