SCC2681 查看數據表（PDF） - NXP Semiconductors.
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SCC2681 Datasheet PDF : 29 Pages
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Philips Semiconductors
Dual asynchronous receiver/transmitter (DUART)
Product data
SCC2681
8. Consecutive write operations to the same command register require at least three edges of the X1 clock between writes.
9. This parameter is not applicable to the 28-pin device.
10. Operation to 0 MHz is assured by design. However, operation at low frequencies is not tested and has not been characterized.
BLOCK DIAGRAM
8
D0–D7
BUS BUFFER
RDN
WRN
CEN
4
A0–A3
RESET
OPERATION CONTROL
ADDRESS
DECODE
R/W CONTROL
INTRN
INTERRUPT CONTROL
IMR
ISR
CHANNEL A
TRANSMIT
HOLDING REG
TRANSMIT
SHIFT REGISTER
RECEIVE
HOLDING REG (3)
RECEIVE
SHIFT REGISTER
MRA1, 2
CRA
SRA
CHANNEL B
(AS ABOVE)
TxDA
RxDA
TxDB
RxDB
X1/CLK
X2
TIMING
BAUD RATE
GENERATOR
CLOCK
SELECTORS
COUNTER/
TIMER
XTAL OSC
CSRA
CSRB
ACR
CTUR
CTLR
INPUT PORT
CHANGE OF
STATE
DETECTORS (4)
IPCR
ACR
OUTPUT PORT
FUNCTION
SELECT LOGIC
OPCR
OPR
Figure 2. Block Diagram
7
IP0-IP6
8
OP0-OP7
VCC
GND
SD00085
2004 Apr 06
7
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