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STP16CPC26(2013) 查看數據表(PDF) - STMicroelectronics

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产品描述 (功能)
生产厂家
STP16CPC26
(Rev.:2013)
ST-Microelectronics
STMicroelectronics 
STP16CPC26 Datasheet PDF : 26 Pages
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Timing diagrams
8
Timing diagrams
STP16CPC26
The timing diagram shown in Figure 11 and the truth table in Table 7 explain how to send
data to the device. This can be summarized in the following points:
LE and OE are level sensitive and not synchronized with the CLK signal
When LE is at low level, the latch circuit holds previous data
If LE is high level, data present in the shift register are latched
When OE is at low level, the status of the outputs OUT0 to OUT15 depends on the data
in the latch circuits
With OE at high level, all outputs are switched off independently on the data stored in
the latch circuits
Every rising edge of the CLK signal, a new data on SDI pin is sampled. This data is
loaded into the shift register, whereas a bit is shifted out from SDO.
Figure 11. Timing diagram
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12/26
Doc ID 18469 Rev 4

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