CY8C5466AXI-064 查看數據表（PDF） - Cypress Semiconductor

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CY8C5466AXI-064

Programmable System-on-Chip (PSoC®)

Cypress Semiconductor 

PRELIMINARY

PSoC® 5: CY8C54 Family Datasheet

PSoC supports a wide range of low power modes. These include

a 300 nA hibernate mode with RAM retention and a 2 µA sleep

mode with RTC. In the second mode the optional 32.768 KHz

watch crystal runs continuously and maintains an accurate RTC.

Power to all major functional blocks, including the programmable

digital and analog peripherals, can be controlled independently

by firmware. This allows low power background processing

when some peripherals are not in use. This, in turn, provides a

total device current of only 2 mA when the CPU is running at

6 MHz.

The details of the PSoC power modes are covered in the “Power

System” section on page 22 of this data sheet.

PSoC uses a a JTAG (4 wire) or SWD (2 wire) interface for

programming, debug, and test. Using these standard interfaces

enables the designer to debug or program the PSoC with a

variety of hardware solutions from Cypress or third party

vendors. The Cortex-M3 debug and trace modules include Flash

Patch and Breakpoint (FPB), Data Watchpoint and Trace (DWT),

Embedded Trace Macrocell (ETM), and Instrumentation Trace

Macrocell (ITM). These modules have many features to help

solve difficult debug and trace problems. Details of the

programming, test, and debugging interfaces are discussed in

the “Programming, Debug Interfaces, Resources” section on

page 54 of this data sheet.

2. Pinouts

The Vddio pin that supplies a particular set of pins is indicated

by the black lines drawn on the pinout diagrams in Figure 2-1 and

Figure 2-2. Using the Vddio pins, a single PSoC can support

multiple interface voltage levels, eliminating the need for off-chip

level shifters. Each Vddio may sink up to 100 mA total to its

associated I/O pins and opamps. On the 68 pin and 100 pin

devices each set of Vddio associated pins may sink up to

100 mA. The 48 pin device may sink up to 100 mA total for all

Vddio0 plus Vddio2 associated I/O pins and 100 mA total for all

Vddio1 plus Vddio3 associated I/O pins.

Document Number: 001-66238 Rev. **

Page 5 of 105

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