CY8C5466AXI-064 查看數據表（PDF） - Cypress Semiconductor

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CY8C5466AXI-064

Programmable System-on-Chip (PSoC®)

Cypress Semiconductor 

PRELIMINARY

PSoC® 5: CY8C54 Family Datasheet

Figure 2-4. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance

Vssa

Vddd

Vssd

Vdda

Vssd

Plane

Vssa

Plane

3. Pin Descriptions

IDAC0, IDAC1, IDAC2, IDAC3

Low resistance output pin for high current DACs (IDAC).

OpAmp0out, OpAmp1out, OpAmp2out, OpAmp3out

High current output of uncommitted opamp[6].

Extref0, Extref1

External reference input to the analog system.

OpAmp0–, OpAmp1–, OpAmp2–, OpAmp3–

Inverting input to uncommitted opamp.

OpAmp0+, OpAmp1+, OpAmp2+, OpAmp3+

Noninverting input to uncommitted opamp.

GPIO

General purpose I/O pin provides interfaces to the CPU, digital

peripherals, analog peripherals, interrupts, LCD segment drive,

and CapSense[6].

Ind. Inductor connection to boost pump.

kHz XTAL: Xo, kHz XTAL: Xi

32.768 KHz crystal oscillator pin.

MHz XTAL: Xo, MHz XTAL: Xi

4 to 25 MHz crystal oscillator pin. If a crystal is not used then Xi

must be shorted to ground and Xo must be left floating.

nTRST. Optional JTAG Test Reset programming and debug port

connection to reset the JTAG connection.

SIO. Special I/O provides interfaces to the CPU, digital

peripherals and interrupts with a programmable high threshold

voltage, analog comparator, high sink current, and high

impedance state when the device is unpowered.

SWDCK

Serial Wire Debug Clock programming and debug port connection.

SWDIO

Serial Wire Debug Input and Output programming and debug

port connection.

TCK. JTAG Test Clock programming and debug port connection.

TDI. JTAG Test Data In programming and debug port

connection.

TDO. JTAG Test Data Out programming and debug port

connection.

TMS. JTAG Test Mode Select programming and debug port

connection.

TRACECLK. Cortex-M3 TRACEPORT connection, clocks

TRACEDATA pins.

TRACEDATA[3:0].

Cortex-M3 TRACEPORT connections, output data.

SWV.

Single Wire Viewer output.

USBIO, D+

Provides D+ connection directly to a USB 2.0 bus. May be used

as a digital I/O pin; it is powered from Vddd instead of from a

Vdddio. Pins are Do Not Use (DNU) on devices without USB.

USBIO, D–

Provides D– connection directly to a USB 2.0 bus. May be used

as a digital I/O pin; it is powered from Vddd instead of from a

Vdddio. Pins are Do Not Use (DNU) on devices without USB.

Notes

6. GPIOs with opamp outputs are not recommended for use with CapSense.

Document Number: 001-66238 Rev. **

Page 9 of 105

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