ISL80101A 查看數據表（PDF） - Intersil
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ISL80101A Datasheet PDF : 11 Pages
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ISL80121-5
Power Dissipation and Thermals
The junction temperature must not exceed the range specified in
the “Recommended Operating Conditions” on page 4. The power
dissipation can be calculated by using Equation 5:
PD = (VIN – VOUT) × IOUT + VIN × IGND
(EQ. 5)
The maximum allowable junction temperature, TJ(MAX) and the
maximum expected ambient temperature, TA(MAX) determine the
maximum allowable power dissipation, as shown in Equation 6:
PD(MAX) = (TJ(MAX) – TA) ⁄ θJA
(EQ. 6)
θJA is the junction-to-ambient thermal resistance.
For safe operation, ensure that the power dissipation PD,
calculated from Equation 5, is less than the maximum allowable
power dissipation PD(MAX).
The DFN package uses the copper area on the PCB as a heat-sink.
The EPAD of this package must be soldered to the copper plane
(GND plane). Figure 13 shows a curve for the θJA of the DFN
package for different copper area sizes.
46
44
42
40
38
36
34
2 4 6 8 10 12 14 16 18 20 22 24
EPAD-MOUNT COPPER LAND AREA ON PCB, mm2
FIGURE 13. 3mmx3mm 10 LD DFN ON 4-LAYER PCB WITH THERMAL
VIAS θJA vs EPAD-MOUNT COPPER LAND AREA ON PCB
Thermal Fault Protection
The power level and the thermal impedance of the package
(+48°C/W for DFN) determine when the junction temperature
exceeds the thermal shutdown temperature. In the event that the
die temperature exceeds around +160°C, the output of the LDO
will shut down until the die temperature cools down to about
+130°C.
General PowerPAD Design Considerations
Figure 14 shows the recommended use of vias on the thermal
pad to remove heat from the IC. This typical array populates the
thermal pad footprint with vias spaced three times the radius
distance from the center of each via. Small via size is advisable,
but not to the extent that solder reflow becomes difficult.
All vias should be connected to the pad potential, with low thermal
resistance for efficient heat transfer. Complete connection of the
plated-through hole to each plane is important. It is not
recommended to use “thermal relief” patterns to connect the vias.
FIGURE 14. PCB VIA PATTERN
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FN7713.4
September 29, 2011
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