AD8114 查看數據表（PDF） - Analog Devices
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AD8114 Datasheet PDF : 32 Pages
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AD8114/AD8115
TIMING CHARACTERISTICS (PARALLEL)
Table 4. Timing Characteristics
Parameter
Data Setup Time
CLK Pulse Width
Data Hold Time
CLK Pulse Separation
CLK to UPDATE Delay
UPDATE Pulse Width
Propagation Delay, UPDATE to Switch On or Off
CLK, UPDATE Rise and Fall Times
RESET Time
Symbol
t1
t2
t3
t4
t5
t6
–
–
–
Min
Typ
20
100
20
100
0
50
Max
Unit
ns
ns
ns
ns
ns
ns
50
ns
100
ns
200
ns
Table 5. Logic Levels
VIH
VIL
RESET, SER/PAR, RESET, SER/PAR,
CLK, D0, D1, D2, CLK, D0, D1, D2,
D3, D4, A0, A1, A2, D3, D4, A0, A1, A2,
A3, CE, UPDATE A3, CE, UPDATE
VOH
DATA OUT
VOL
DATA OUT
2.0 V min
0.8 V max
2.7 V min 0.5 V max
IIH
RESET, SER/PAR,
CLK, D0, D1, D2,
D3, D4, A0, A1, A2,
A3, CE, UPDATE
20 µA max
IIL
RESET, SER/PAR,
CLK, D0, D1, D2,
D3, D4, A0, A1, A2,
A3, CE, UPDATE
−400 µA min
IOH
DATA
OUT
−400 µA
max
IOL
DATA
OUT
3.0 mA
min
1
CLK
0
1
D0–D3
A0–A2
0
1 = LATCHED
UPDATE
0 = TRANSPARENT
t2
t4
t1
t3
Figure 3. Timing Diagram, Parallel Mode
t5 t6
Rev. B | Page 6 of 32
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