NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
Table 2.
Symbol
CP0
MR
VDD
Pin description …continued
Pin
14
15
16
7. Functional description
Description
clock input (LOW-to-HIGH edge-triggered)
master reset input
supply voltage
Table 3. Function table [1]
MR
CP0
CP1
H
X
X
L
H
↓
L
↑
L
L
L
X
L
X
H
L
H
↑
L
↓
L
Operation
Q0 = Q5-9 = H; Q1 to Q9 = L
counter advances
counter advances
no change
no change
no change
no change
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;
↑ = positive-going transition; ↓ = negative-going transition.
HEF4017B_4
Product data sheet
Rev. 04 — 9 December 2008
© NXP B.V. 2008. All rights reserved.
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