WM8960 查看數據表（PDF） - Wolfson Microelectronics plc

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产品描述 (功能)

生产厂家

WM8960

Stereo CODEC with 1W Stereo Class D Speaker Drivers and Headphone Drivers for Portable Audio Applications

Wolfson Microelectronics plc 

Production Data

SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK TIMING

WM8960

MCLK

tMCLKY

Figure 2 System Clock Timing Requirements

Test Conditions

DCVDD=1.8V, DBVDD=AVDD=SPKVDD1=SPKVDD2=3.3V, DGND=AGND=SPKGND1=SPKGND2=0V, TA = +25oC

PARAMETER

System Clock Timing Information

MCLK cycle time

MCLK duty cycle

SYMBOL

TMCLKY

TMCLKDS

CONDITIONS

MIN

33.33

60:40

TYP

MAX

40:60

UNIT

ns

AUDIO INTERFACE TIMING – MASTER MODE

Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)

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PD, August 2013, Rev 4.2

13

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