HT47C20L 查看數據表（PDF） - Holtek Semiconductor

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HT47C20L

R-F Type Low Voltage 8-Bit Mask MCU

Holtek Semiconductor 

stack pointer (SP) and is neither readable nor writeable.

At a subroutine call or interrupt acknowledgment, the

contents of the program counter are pushed onto the

stack. At the end of a subroutine or an interrupt routine,

signaled by a return instruction (RET or RETI), the pro-

gram counter is restored to its previous value from the

stack. After a chip reset, the SP will point to the top of the

stack.

If the stack is full and a non-masked interrupt takes

place, the interrupt request flag will be recorded but the

acknowledgment will be inhibited. When the stack

pointer is decremented (by RET or RETI), the interrupt

will be serviced. This feature prevents stack overflow al-

lowing the programmer to use the structure more easily.

In a similar case, if the stack is full and a ²CALL² is sub-

sequently executed, stack overflow occurs and the first

entry will be lost (only the most recent four return ad-

dresses are stored).

Data Memory - RAM

The data memory is designed with 83´8 bits. The data

memory is divided into two functional groups: special

function registers and general purpose data memory

(64´8). Most are read/write, but some are read only.

The special function registers include the indirect address-

ing register 0 (00H), the memory pointer register 0 (MP0;

01H), the indirect addressing register 1 (02H), the memory

pointer register 1 (MP1;03H), the bank pointer (BP;04H),

the accumulator (ACC;05H), the program counter

lower-order byte register (PCL;06H), the table pointer

(TBLP;07H), the table higher-order byte register

(TBLH;08H), the real time clock control register

(RTCC;09H), the status register (STATUS;0AH), the inter-

rupt control register 0 (INTC0;0BH), the I/O registers

(PA;12H, PB;14H), the interrupt control register 1

(INTC1;1EH), the Timer/Event counter A higher order byte

register (TMRAH; 20H), the Timer/Event Counter A lower

order byte register (TMRAL; 21H), the timer/event counter

control register (TMRC; 22H), the Timer/Event Counter B

higher order byte register (TMRBH; 23H), the Timer/Event

Counter B lower-order byte register (TMRBL; 24H), and

the RC oscillator type A/D converter control register

(ADCR; 25H). The remaining space before the 40H are

reserved for future expanded usage and reading these

location will return the result 00H. The general purpose

data memory, addressed from 40H to 7FH, is used for

data and control information under instruction com-

mand.

All data memory areas can handle arithmetic, logic, in-

crement, decrement and rotate operations. Except for

some dedicated bits, each bit in the data memory can be

set and reset by the ²SET [m].i² and ²CLR [m].i² instruc-

tion, respectively. They are also indirectly accessible

through memory pointer registers (MP0;01H,

MP1;03H).

HT47C20L

0 0 H In d ir e c t A d d r e s s in g R e g is te r 0

01H

MP 0

0 2 H In d ir e c t A d d r e s s in g R e g is te r 1

03H

M P1

04H

BP

05H

ACC

06H

PCL

07H

TB LP

08H

TB LH

09H

R TC C

0A H

STATU S

0B H

IN T C 0

0C H

0D H

0E H

0FH

10H

11H

12H

PA

13H

14H

PB

15H

16H

17H

18H

19H

1A H

1B H

1C H

1D H

1E H

IN T C 1

1FH

20H

TM R AH

21H

TM R AL

22H

TM R C

23H

TM R BH

24H

TM R BL

25H

ADCR

26H

S p e c ia l P u r p o s e

D a ta M e m o ry

:U nused

3FH

40H

G e n e ra l P u rp o s e

D a ta M e m o ry

(6 4 B y te s )

R e a d a s "0 0 "

7FH

RAM Mapping (Bank 0)

Indirect Addressing Register

Location 00H and 02H are indirect addressing registers

that are not physically implemented. Any read/write op-

eration of [00H] and [02H] access data memory pointed

to by MP0 (01H) and MP1 (03H) respectively. Reading

location 00H or 02H indirectly will return the result 00H.

Writing indirectly results in no operation.

Rev. 2.30

9

December 2, 2005

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