SG6846A 查看數據表（PDF） - Fairchild Semiconductor
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SG6846A Datasheet PDF : 15 Pages
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(1 ) Normal
operation
(4)
VDD< 12 V ?
NO
YES
NO
(2)
IP > 2 /3 IPK ?
(3)
Timing = 100 ms
(5)
Timing = 1700 ms
(6 ) NO
YES VDD< = 12 V ?
SCP
OCP
(7 ) Gate off
SCP
Figure 6. SG6846A OCP/SCP Logic Flow Diagram
Electrical Characteristics (Continued)
VDD = 15V and TA = 25°C unless otherwise noted.
Symbol
Parameter
Oscillator Section
fOSC
Normal PWM Frequency
Center
Frequency
Jitter Range
fOSC,MAX
Maximum PWM
Frequency
Center
Frequency
Jitter Range
fOSC,MIN
Center
Minimum PWM Frequency Frequency
Jitter Range
thop-1
thop-3
fOSC-G
VFB-N
VFB-G
SG
fDV
fDT
Jitter Period
Green-Mode Minimum Frequency
FB Pin Frequency Pin, FB voltage
Reduction Threshold Jitter Range
Pin, FB voltage
FB Voltage at fOSC-G
Jitter Range
Slope for Green-Mode Modulation
Frequency Variation vs. VDD Deviation
Frequency Variation vs. Temperature
Deviation
Test Condition Min. Typ. Max. Unit
RI = 26kΩ, VFB>VN
62
65
68
kHz
±3.7 ±4.2 ±4.7
RI = 13kΩ, VFB>VN
124 130 136
kHz
±7.4 ±8.4 ±9.4
RI = 36kΩ, VFB>VN
RI = 26kΩ, VFB ≥ VN
RI = 26kΩ, VFB = VG
RI = 26kΩ
RI = 26kΩ, VFB = VN
RI = 26kΩ, VFB = VG
RI = 26kΩ
VDD = 11.5V to 20V
44.8
±2.54
3.9
10.2
18.0
1.9
3.7
1.4
1.27
47.0
±2.90
4.4
11.5
22.5
2.1
4.2
1.6
1.45
85
49.2
kHz
±3.26
4.9
ms
12.8
25.0 kHz
2.3
V
4.7 KHz
1.8
V
1.62 KHz
Hz/mV
5
%
TA = -30 to 85°C
1.5
5.0
%
Continued on following page…
© 2008 Fairchild Semiconductor Corporation
SG6846A • Rev. 1.1.4
7
www.fairchildsemi.com
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