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CY8C26443-24PI 查看數據表(PDF) - Cypress Semiconductor

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CY8C26443-24PI Datasheet PDF : 148 Pages
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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
1.0 Functional Overview
The CPU heart of this next generation family of micro-
controllers is a high performance, 8-bit, M8C Harvard
architecture microprocessor. Separate program and
memory busses allow for faster overall throughput. Pro-
cessor clock speeds to 24 MHz are available. The pro-
cessor may also be run at lower clock speeds for power-
sensitive applications. A rich instruction set allows for
efficient low-level language support.
All devices in this family include both analog and digital
configurable peripherals (PSoC blocks). These blocks
enable the user to define unique functions during config-
uration of the device. Included are twelve analog PSoC
blocks and eight digital PSoC blocks. Potential applica-
tions for the digital PSoC blocks are timers, counters,
UARTs, CRC generators, PWMs, and other functions.
The analog PSoC blocks can be used for SAR ADCs,
Multi-slope ADCs, programmable gain amplifiers, pro-
grammable filters, DACs, and other functions. Higher
order User Modules such as modems, complex motor
controllers, and complete sensor signal chains can be
created from these building blocks. This allows for an
unprecedented level of flexibility and integration in micro-
controller-based systems.
A Multiplier/Accumulator (MAC) is available on all
devices in this family. The MAC is implemented on this
device as a peripheral that is mapped into the register
space. When an instruction writes to the MAC input reg-
isters, the result of an 8x8 multiply and a 32-bit accumu-
late are available to be read from the output registers on
the next instruction cycle.
The number of general purpose I/Os available in this
family of parts range from 6 to 44. Each of these I/O pins
has a variety of programmable options. In the output
mode, the user can select the drive strength desired.
Any pin can serve as an interrupt source, and can be
selected to trigger on positive edges, negative edges, or
any change. Digital signal sources can be routed directly
from a pin to the digital PSoC blocks. Some pins have
additional capability to route analog signals to the analog
PSoC blocks.
Multiple oscillator options are available for use in clock-
ing the CPU, analog PSoC blocks and digital PSoC
blocks. These options include an internal main oscillator
running at 48/24 MHz, an external crystal oscillator for
use with a 32.768 kHz watch crystal, and an internal low-
speed oscillator for use in clocking the PSoC blocks and
the Watchdog/Sleep timer. User selectable clock divisors
allow for optimizing code execution speed and power
trade-offs.
The different device types in this family provide various
amounts of code and data memory. The code space
ranges in size from 4K to 16K bytes of user programma-
ble Flash memory. This memory can be programmed
serially in either a programming Pod or on the user
board. The endurance on the Flash memory is 50,000
erase/write cycles. The data space is 256 bytes of user
SRAM.
A powerful and flexible protection model secures the
user’s sensitive information. This model allows the user
to selectively lock blocks of memory for read and write
protection. This allows partial code updates without
exposing proprietary information.
Devices in this family range from 8 pins through 48 pins
in PDIP, SOIC and SSOP packages.
1.1 Key Features
Table 1: Device Family Key Features
Operating Frequency
Operating Voltage
Program Memory (KBytes)
Data Memory (Bytes)
Digital PSoC Blocks
Analog PSoC Blocks
I/O Pins
External Switch Mode Pump
Available Packages
CY8C25122
93.7kHz - 24MHz
3.0 - 5.25V
4
256
8
12
6
No
8 PDIP
CY8C26233
93.7kHz - 24MHz
3.0 - 5.25V
8
256
8
12
16
Yes
20 PDIP
20 SOIC
20 SSOP
CY8C26443
93.7kHz - 24MHz
3.0 - 5.25V
16
256
8
12
24
Yes
28 PDIP
28 SOIC
28 SSOP
CY8C26643
93.7kHz - 24MHz
3.0 - 5.25V
16
256
8
12
40/44
Yes
48 PDIP
48 SSOP
44 TQFP
14
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002

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