EVAL-ADV7194EB 查看數據表（PDF） - Analog Devices

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EVAL-ADV7194EB

Evaluation Board for the ADV7194 Digital Video Encoder

Analog Devices 

LINK HEADERS

ADV7194 LINKS

These links are used for operating the ADV7194

encoder:

J1

Ground link

J2

Link clock signal to header P2.

J3

Ground link

J4, J6 Link Pull-Down Resistors (2K2) of

8/10-bit pixel input to Ground.

J8

Clock Mode

J8A: ADV7194 is clocked from the on-

board 27Mhz clock.

J8B : ADV7194 is clocked from the

clock contained in the pixel input.

J9, J12 If U10 (IC570) is used as an

external PLL (as an alternative to the

internal PLL).

J12A provides the 27Mhz input clock

and

J9A provides the 54Mhz clock to the

ADV7194.

J10 Link clock signal to CLKIN pin of the

ADV7194 and bypass the external PLL

circuitry.

J19 Link ALSB pin to Ground. This jumper

should be inserted when ALSB is chosen

to be set low.

Eval-ADV7194EB

J20 Link BLANK pin to Ground. This allows

control over the BLANK pin functionality

over the software. If unconnected the

BLANK pin is disabled permanently and

the software can not control the BLANK

pin functionality.

J21 Link PAL_NTSC pin to Ground. Inserting

this jumper will configure the ADV7194 to

run in NTSC mode regardless of the

settings in Mode Register 0. The settings in

Mode Register 2 can however override this

pin (Standard I2C Control).

J22 Timing Reset or SCReset / PB2

J22A:

J22B:

The SCRESET/RTC/TR pin and

PB2 are configured as a Timing

Reset.

The SCRESET/RTC pin is

configured as a subcarrier phase

reset input pin or as a RTC input

pin, according to the settings in

Mode Register 4. When Mode

Register 4 is configured in

Subcarrier Reset mode, PB2 will

initiate a Subcarrier Phase reset

and the Subcarrier Phase will reset

to Field 0 at the start of the next

Field.

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