CD40108BMS 查看數據表（PDF） - Intersil
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CD40108BMS Datasheet PDF : 11 Pages
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CD40108BMS
1
2
3
Q
4
5
1kΩ
6
TO ANY
7
OUTPUT
8
50pF
9
10
11
12
24
PULSE
GEN. 2
23
P.G. 1
CL
22
21
20
19
D
18
17
16
PULSE
GEN. 1
15
14
P.G. 2
ENABLE
INPUT 50%
tPLZ
Q
OUTPUTS
tPHZ
ENABLE
10%
90%
VDD
50%
VSS
tPZL
90%
VDD
VOL
VOH
10%
VSS
tPZH
13
TEST VOLTAGE
CHAR AT D
AT Q
tPHZ
tPZH
VDD
VDD
VSS
VSS
tPLZ
VSS
VDD
tPZL
VSS
VDD
FIGURE 12. OUTPUT-ENABLE-DELAY-TIMES TEST CIRCUIT AND WAVEFORMS
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
7-35
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